Circuit characterization and Performance Estimation

1. Circuit characterization and Performance Estimation

2. Introduction • Need simple models to estimate system performance in terms of signal delay and power dissipation. • Each layer in an MOS transistor has both resistance and capacitance that are fundamental components in estimating the performance of a circuit or system. • They also have inductance characteristics that is assumed to be negligible.

3. Introduction • Issues include: • Resistance, capacitance and inductance calculations. • Delay estimations. • Determination of conductor size for power and clock distribution. • Power consumption. • Charge sharing mechanisms. • Design Margining. • Reliability. • Effects of scaling.

4. Resistance Estimation The resistance of a uniform slab of conducting material may be expressed as: Alternatively as

5. Choice of Metals • Until 180 nm generation, most wires were aluminum • Modern processes often use copper • Cu atoms diffuse into silicon and damage FETs • Must be surrounded by a diffusion barrier

6. Sheet Resistance Typical sheet resistance values for materials are very well characterized Typical Sheet Resistances for 5µm Technology

7. Sheet Resistance Note: L defined parallel to current and W defined perpendicular to current.

8. Sheet Resistance

9. Rs for poly is 4 /square in 1micron tech. Rpoly = 4 /square x (19/3 + 11/4 + 19/3) squares = 61.6 . A note: A corner square has a sheet resistance of ~0.5 Rs.

10. Example:R = Rs(poly) * 13 + 2*(1/2) + 3*(1/2) squaresR = 4Ω/sq * 15.5 squares = 62Ω Corner (1/2 Square) 1/2 Square 1/2 Square Corner (1/2 Square) Corner (1/2 Square) Example

11. Resistance Estimation Channel resistance can be estimated in the linear region as: A range of 1,000 to 30,000 ohms/square are possible for n-channel and p-channel devices. • Temperature changes both  (mobility) and Vt (threshold voltage) and therefore channel resistance. • Channel resistance increases with temperature, approximately +0.25% per degree C above 25 degrees. • Metal and poly resistance change about 0.3% and well diffusions about 1% per degree C.

12. Capacitance Estimation • Switching speed of MOS systems stronglydependent: • Parasitic capacitances associated with the MOS transistor. • Interconnect capacitance of "wires". • Resistance of transistors and wires. • Total loadcapacitance on the output of a CMOS gate is sum of: • Gate capacitance (of receiverlogic gates downstream). • Driverdiffusion (source/drain) capacitance. • Routing (line) capacitance of substrate and other wires.

13. MOS Capacitor Characteristics • The capacitance-voltage characteristics of an MOS structure depend on the state of the semiconductor surface. • Depending on gate voltage, the surface may be in : accumulation depletion inversion

14. In deletion mode MOS Capacitor Characteristics In accumulation:

15. MOS Capacitor Characteristics In inversion mode:

16. Diagrammatic representation of parasitic Capacitances of MOS • The capacitance of a MOS transistor can be modeled using 5 capacitors • The overlap of gate over the drain and source is assumed to be zero. • An approximation of gate capacitance (Cgs, Cgdand Cgb) is given as:

17. Estimating Gate Capacitance For example, for thin-oxide thickness of 15 nm In  = 0.5 technology, W = 2 and L = 1 This is a conservative estimate of gate capacitance that does not include fringing fields (extrinsic) gate capacitance. Gate capacitance increases as the thin-oxide thins.

18. The total gate Capacitance

19. The total gate Capacitance The total gate Capacitance as a function of Vgs The overall gate capacitance (for an n-device) is approximately equal to the intrinsic “gate-oxide” capacitance for all values of gate voltage except for voltages around the threshold voltage of the transistor, Vt

20. Circuit symbol for parasitic Capacitance

21. Estimating Source/Drain Capacitance This model assumes a zero DC bias across the junction.

22. Estimating Source/Drain Capacitance

23. n-channel device Estimating Source/Drain Capacitance For example: Typical values for 0.5 micron process Because of fan-out, gate capacitance usually dominates the loading.

24. Estimating Routing Capacitance Routing capacitance between metal and poly can be approximated using a parallel-plate model. • The parallel-plate model approximation ignores fringing fields. • The effect of the fringing fields is to increase the effective area of the plates. • Consequently, poly and metal lines will actually have a higher capacitance than that predicted by the model. • As line widths are scaled, the width (w) and heights of wires tend to reduce less than their separations. • Accordingly, this fringing effect increases in importance.

25. Estimating Routing Capacitance C=Cplate*area+CFringe*peripheral Example: Poly: Cplate-poly*12*4+Cfringe-poly*2*(12+4)  Metal:Cplate-metal1*12*4+Cfringe-metal1*2*(12+4) 

26. Estimating Capacitance Example: Cg=4 * 2  Cox CPoly=2* (2  * 2 ) Cpoly (plate) + 2* (2 + 2 + 2)  Cpoly (fringe)

27. Estimating Capacitance Example: Cنفوذ=[12 *3  + 4 *4  ]* Cنفوذ(plate) + (3 +12 + 1 + 4 +4+16 ) * cجانبی-نفوذ Cفلز=6  * 10  * C(plate)+ 2*(6 + 10)  * C (fringe) Cکل= Cنفوذ + Cفلز

28. Multilayer capacitance calculations Example: given the layout shown in the figure calculate the total capacitance at source and gate given that: Ignore Fringing Capacitance

29. Solution

30. Example

31. Example

32. Example What are the parasitic capacitances visible from point “A”?

33. Example

34. Diffusion Parasitics Capacitance

35. Parasitics on 2-input NAND • How can we estimate Cpdiff and Cndiff?

36. NAND Layout

37. NAND Layout

38. Diffusion Parasitics - Summing Up = 6.465fF = 0.725fF

39. Delay in Long Wires - Lumped RC Model • What is the delay in a long wire? • Lumped RC Model: • Delay time constant (ignoring driving gate) t = R * C = (Rs * L / W) * (L * W * Cplate )= r * c * L2 R = Rs * L / W = r*L (r = Rs / W - resistance per unit length ) C = L * W * Cplate = c*L(c = W * Cplate - capacitance per unit length)

40. R Vout Vin C Wire Delay Models • Lumped RC Model • Total wire resistance is lumped into a single R and total capacitance into a single C • Good for short wires; pessimistic and inaccurate for long wires Vout(t) = VDD(1-exp(-t/RC)) V50%(t) = VDD(1-exp(-PLH/RC)) τPLH ≈0.69RC

41. R/2 R/2 Vin Vout C Wire Delay Models • T-Model • The above simple lumped RC model can be significantly improved by the T-model as - model This model is used in Elmore Model

42. Delay in Long Wires -Distributed RC Model • Alternative: Break wire into small segments • Approx. Solution - 1st moment of impulse response • Important: delay still grows as square of length

43. Example • Metal2 wire in 180 nm process • 5 mm long • 0.32 mm wide • R = 0.05 W/, Cpermicron = 0.2 fF/mm • Construct a 3-segment p-model • R = 0.05 W/ R= R *(5x10-3/0.32 mm ) => R = 781 W • Cpermicron = 0.2 fF/mm C= 0.2 fF/mm x 5x10-3 => C = 1 pF

47. Elmore Delay Model

48. Elmore Delay • ON transistors look like resistors • Pullup or pulldown network modeled as RC ladder • Elmore delay of RC ladder

49. The Elmore Delay Estimation Technique