Introduction to CMOS VLSI Design Circuit Characterization and Performance Estimation

1. Introduction toCMOS VLSIDesignCircuit Characterization and Performance Estimation

2. Outline • Noise Margins • Transient Analysis • Delay Estimation • Logical Effort and Transistor Sizing

3. Noise Margins • How much noise can a gate input see before it does not recognize the input?

4. Logic Levels • To maximize noise margins, select logic levels at

5. Logic Levels • To maximize noise margins, select logic levels at • unity gain point of DC transfer characteristic

6. Transient Response • DC analysis tells us Vout if Vin is constant • Transient analysis tells us Vout(t) if Vin(t) changes • Requires solving differential equations • Input is usually considered to be a step or ramp • From 0 to VDD or vice versa

7. Inverter Step Response • Ex: find step response of inverter driving load cap

8. Inverter Step Response • Ex: find step response of inverter driving load cap

9. Delay Definitions • tpd: propagation delay time • maximum time from input crossing 50% to output crossing 50% • tcd: contamination delay time • minimum time from input crossing 50% to output crossing 50% • trf = (tr + tf )/2 • tr: rise time • From output crossing 0.2 VDD to 0.8 VDD • tf: fall time • From output crossing 0.8 VDD to 0.2 VDD

10. Delay Definitions • tcdr: rising contamination delay • From input crossing VDD/2 to rising output crossing VDD/2 • tcdf: falling contamination delay • From input crossing VDD/2 to falling output crossing VDD/2 • tcd: average contamination delay • tcd = (tcdr + tcdf)/2

11. Simulated Inverter Delay • Solving differential equations by hand is too hard • SPICE simulator solves the equations numerically • Uses more accurate I-V models too! • But simulations take time to write

12. Delay Estimation • We would like to be able to easily estimate delay • Not as accurate as simulation • But easier to ask “What if?” • The step response usually looks like a 1st order RC response with a decaying exponential. • Use RC delay models to estimate delay • C = total capacitance on output node • Use effective resistance R • So that tpd = RC • Characterize transistors by finding their effective R • Depends on average current as gate switches

13. RC Delay Models • Use equivalent circuits for MOS transistors • Ideal switch + capacitance and ON resistance • Unit nMOS has resistance R, capacitance C • Unit pMOS has resistance 2R, capacitance C • Capacitance proportional to width • Resistance inversely proportional to width

14. Example: 3-input NAND • Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R).

15. Example: 3-input NAND • Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R).

16. Example: 3-input NAND • Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R).

17. 3-input NAND Caps • Annotate the 3-input NAND gate with gate and diffusion capacitance.

18. 3-input NAND Caps • Annotate the 3-input NAND gate with gate and diffusion capacitance. Cg is approximately equal to Cdiff in many processes.

19. In a good layout, diffusion nodes are shared wherever possible to reduce the diffusion capacitance The uncontacted diffusion nodes between series transistors are smaller than the contacted diffusion nodes.

20. 3-input NAND Caps • Annotate the 3-input NAND gate with gate and diffusion capacitance.

21. Elmore Delay • ON transistors look like resistors • Pullup or pulldown network modeled as RC ladder • Elmore delay of RC ladder

22. Example: 2-input NAND • Estimate worst-case rising and falling delay of 2-input NAND driving h identical gates.

23. Example: 2-input NAND • Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates.

24. Example: 2-input NAND • Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates.

25. Example: 2-input NAND • Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates.

26. Example: 2-input NAND • Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates.

27. Estimate the worst case falling propagation delays of a 2-input NAND driving h identical gates The worst case occurs when the node x is already charged up to nearly Vdd through the top nMOS Suppose A = 1, B = 0, then Y = 1, node X is nearly VDD Now change inputs to A=B=1 both node Y and node X need to discharge

28. Example: 2-input NAND • Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates.

29. Example: 2-input NAND • Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates.

30. Delay Components • Delay has two parts • Parasitic delay, gate driving its own internal diffusion capacitance • 6 or 7 RC • Independent of load • Effort delay, depends on the ration of external load capacitance to input capacitance, • Effort delay changes with transistor width • Proportional to load capacitance • Logical effort and Electrical effort

31. Contamination Delay • Best-case (contamination) delay can be substantially less than propagation delay. • Ex: If both inputs fall simultaneously, the output should be pulled up in half the time tcdr = (R/2)(6+4h)C

32. Diffusion Capacitance • we assumed contacted diffusion on every s / d. • Good layout minimizes diffusion area • Ex: NAND3 layout shares one diffusion contact • Reduces output capacitance by 2C • Merged uncontacted diffusion might help too

33. Layout Comparison • Which layout is better?