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1 - Progress report on the E CAL prototype 2 - New informations on the cost of the W-Si ECAL

News of the CALICE - ECAL. Sampling calorimeter tungsten-silicon. 1 - Progress report on the E CAL prototype 2 - New informations on the cost of the W-Si ECAL 3 - A proposal for a new design of the detector slab 4 - Conclusion. Progress report on the prototype. Mid-march

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1 - Progress report on the E CAL prototype 2 - New informations on the cost of the W-Si ECAL

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  1. News of the CALICE - ECAL Sampling calorimeter tungsten-silicon 1 -Progress report on the ECAL prototype 2 -New informations on the cost of the W-Si ECAL 3 -A proposal for a new design of the detector slab 4 - Conclusion

  2. Progress report on the prototype Mid-march  A first sample of tungsten plates arrives at LLR => metrology The design of the front-end chip is fixed. First batch for test. End-march  Production of the final set of masks for the silicon wafers processing Beginning-April  Start the production of a sample of 40 tungsten plates corresponding to the first technological test and first stack of prototype April-May  Processing of the first 25 silicon wafers (DC coupled) May-September  Processing and test of about 100 silicon wafers  Final submission of the VFE chip for the prototype

  3. Metrology of the first 3 tungsten plates made at LLR It confirms the good quality of the plates As measured at IHEP and ITEP

  4. Technological prototype – detector slab • Second configuration : using PCB solution + internal Frond End Front End electronics Silicon wafer Cooling system Aluminium (C / W) structure type H Signals output PCB

  5. Physics prototype – detector slab • PCB and Front End electronics details : Silicon wafer PCB Flexible circuit Composite Tungsten max 4.5 mm Front End electronics Possible thickness for Front End electronics in this case : 4.5 mm

  6. Physics prototype – cosmic tests - Measurement surface : 128128 mm - Precision : 0.5 mm 1st X-Y line (scintillating fibers) 1 mm Cross-section Detector slab 2nd X-Y line (scintillating fibers) 4 silicon wafer tested

  7. About the cost of the W-Si ECAL Some interesting distributions (updated recently) Moore's Law for Silicon Microstrip Detectors ~ 2000 m² Silicon Area (m²) 1000 CMS 100 GLAST ATLAS 10 NOMAD DO AMS01 CDF 1 LEP CDF 0.1 DATA From H.F-W. Sadrozinski, UC-Santa Cruz

  8. New elements for the cost of the ECAL Cost<< 2$/cm² WARNING : cost (2010) < 2 $/cm²is for microstrip Processing (Guestimate from H.S.) Moore's Law for Silicon Detectors 50 BUT for ECAL W-Si 4'' Wafer size 6'' ¨Number of masks (x 0.5 ) ¨Industrial Yield (x 2 ) ¨use of 8'' wafers ? cost/area ($/cm²) 10 Used in the TDR At least a factor 2 cheaper is expected ß < 2 $/cm² 2 Blank wafer price 6'' 1 DATA From H.F-W. Sadrozinski, UC-Santa Cruz

  9. Re-calculate the estimation of cost, using the2 €/cm²for the silicon The cost of the ECAL is between 68 (20 layers) to99(40layers) M€ With the HCAL (i.e. version DHCAL) , the total cost of the calorimeter ranges from 129(20 layers) to175(40 layers) MCH (CMS equivalent is 145 MCH) 1 -For the complete set ECAL + HCAL + Muon-CH ( MCH) 2 -The change of the geometry can further reduce the cost (length of barrel, internal radius,...) 18/40% reduction CMS 216 Calice -FLC 132/178

  10. Proposal for a new design of the detector slab Why ?  There is a very small available space for the VFE board (0.2x1x2cm³)  Number of bonding/cm on the VFE board (about 160/cm)    Some risk of pick-up noise (EMC) (coherent noise with32 Mchannels)    Number of wires/lines per cm in the flex (from diodes to VFE)    Industrial feasibility for these processesseems difficult   COST What else ? START from usual electronics industrial processes 1 - Use PCBwith low density readout strip 2 - Keepindustrial yield of the silicon diodes as high as possible 3 - Keep thesmall thicknessof the total 4 - Keep thepad size open(from 0.5 to 1.5 cm) (SD, LD, ...or Rext. TPC)

  11. Point 1Multiplexing inside the alveolus VFE chip inside PCB low densitycooling inside ?? My commentsUP to 200cm PCB low density is quasi-INDUSTRIAL (130 cm is already in the box) Point 2  VFE and Si wafer have independent fabrication process Industrial Yield(VFE is not ``bump bonded'' on the wafer) VFE chip on one side of PCB and diodes on the other My comments - No thermal dissipation through the silicon wafer - Put a silicon wafer on one side and VFE chip on the other side is INDUSTRIAL Point 3  Thin packaging , large area VFE chip Small overall thickness My comments Thickness of the VFE-chip packaging 1mm is INDUSTRIAL Point 4 The pad size depends on the power/channel , cooling system Adaptable pad sizeand duty cycle of the VFE My comments The pad size can be as low as 0.5 cm

  12. Calculation byJ.Badier (LLR) With5mW/c(which not so easy...) 1 -A cooling is NEEDED(at the middle of a module , DT 400°) 2 - It is not so demanding for the thickness Rectangular tube 1mm x 20 mm bar/m D°K

  13. Transverse view - New design of the detector slab - ECAL AC coupling elements if needed Budget (mm) 0.3 Al(sup) 0.1 Glue 1.0 VFE Thermal contact if needed Aluminium 0.3 mm Cooling tube Cooling tube VFE chip 1.1 mm  2-3 cm powerline command line signal out 1.0 mm PCB Pad 0.5 mm Silicon wafer Conductive glue for electrical contact

  14. Advantages and drawbacks Advantages  A priori, all processes are uncorrelated (Si wafer , VFE chip , PCB,...) we could expect a good Industrial Yield  A priori, all processes are (quasi-) industrial  The mounting of the detector slab is a classical job for electronics industrial  Probably easier access to VFE board (not so trivial argument)  Technically, There are interesting challenges, BUT there are no orders of magnitude to gain Almost feasible today Drawbacks What is the behaviour of a VFE chip when a 400 GeV e.m. Shower goes through ?? Could (and will) be rapidly tested

  15. Conclusions Progress report on the prototype  Tungsten, first plates arrived, first sample soon in production Silicon wafers, final masks have been designed VFE chip is in production for the first batch (test) Costing of the calorimeter for FLC  The project is in the extrapolation of the Moore'slaw for the cost and area of silicon to be processed Very probably, the processed silicon wafers will be <2$/cm ²  Even withW-Si ECAL, there is an important cost reduction when compared to the equivalent in CMS CALICE Collaboration New design of the detector slab A lot of advantages - INDUSTRIAL processes The extrapolation from VFE chip is reasonable The extrapolation for the readout lines is reasonable

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