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Computer Science 210 Computer Organization

Computer Science 210 Computer Organization. The Instruction Execution Cycle. Program Development. Create source code. Editor. Compiler. Translate to machine code. Linker. Add library code. Loader. Place code in appropriate memory locations. Runtime System. Execute code.

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Computer Science 210 Computer Organization

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  1. Computer Science 210Computer Organization The Instruction Execution Cycle

  2. Program Development Create source code Editor Compiler Translate to machine code Linker Add library code Loader Place code in appropriate memory locations Runtime System Execute code

  3. Runtime System: Execution Cycle Memory (array of instructions) 0010011100111100 Fetch Load instruction from memory 1000011100110100 0000011100110100 0010011100110100 Decode Figure out what to do 0000011100110101 0100011100110100 Execute Do it This cycle repeats until a HALT instruction is reached

  4. A Machine Language Instruction • Specifies an opcode and one or more operands • The control unit interprets the sequence of bits and sends a sequence of control signals to other units Opcode Operand(s)

  5. Example: LC-3 ADD Instruction Each instruction has a four-bit opcode in bits [15:12] This instruction also specifies two source registers and one destination register Format: Code: Add the contents of R2 and R6 and store the result in R6

  6. LDR (Load Data Relative) Instruction Sign-extend the Offset value to 16 bits, add it to the contents of the Base register, and load the datum at the resulting memory address into the Dst register Format: Code: Load the contents of memory at address (R3 + 6) into R2

  7. The LC-3 Instruction Set (page 119) • 4 bits per opcode, 16 distinct opcodes • But some instructions share an opcode • Example: • So, actually 20 distinct instructions ADD DR SR1 SR2, when bit 5 is clear ADD DR SR1 IR[4:0], when bit 5 is set

  8. Types of Instructions • Computation: ADD, AND, etc. • Data movement: LDR, etc. • Control: BR, JMP, JSR, etc. • Complete set in Table 5.3, page 119 of text

  9. Detailed View of Instruction Processing Fetch Fetch Decode Decode Execute Evaluate address Fetch operands Execute operation Store result

  10. Instruction Processing: Fetch Fetch Load next instruction into IR from memory at address in PC: Decode MAR = PC Send read signal to memory IR = MDR Evaluate address Fetch operands Then increment address in PC Execute operation Store result

  11. Instruction Processing: Decode Fetch Identify the opcode: Bits [15:12] in LC-3 4-to-16 decoder asserts a control line Decode Evaluate address Depending on the opcode, identify the other operands from the remaining bits Fetch operands For the first ADD, bits [11:9] = Destination register bits [8:6] = Source register 1 bits [2:0] = Source register 2 Execute operation Store result

  12. Instruction Processing: Evaluate Address Fetch For instructions with memory access, compute the address used for access Decode Add offset to base register Add offset to PC Add offset to zero Etc. Evaluate address Fetch operands Execute operation Store result

  13. Instruction Processing: Fetch Operands Fetch Obtain the operands needed for the operation Decode Load data from memory (LDR) Read data from register file (ADD) Etc. Evaluate address Fetch operands Execute operation Store result

  14. Instruction Processing: Execute Operation Fetch Perform the operation using the operands Decode Send operands to ALU and assert the ADD signal Do nothing (for LOAD and STORE) Etc. Evaluate address Fetch operands Execute operation Store result

  15. Instruction Processing: Store Result Fetch Write results to destination (register or memory): Decode To destination register (ADD, LDR) For STORE instruction, Evaluate address Write address to MAR Write data to MDR Assert write signal to memory Fetch operands Execute operation Store result

  16. Changing the Sequence of Instructions • Fetch increments the PC by 1 • Loops, if-statements, procedure calls don’t do this • Control instructions modify the PC directly • Jumps: unconditional, always taken • Branches: conditional, depend on contents of status registers

  17. The JMP Instruction Set the PC to the address contained in a register This register is specified in IR[8:6] Format: Code: Load the contents of R3 into the PC

  18. The Control Unit The control unit is a finite state machine; a simplified view:

  19. Stopping the Computer As long as the clock is running, the execution cycle continues If not processing instructions in your program, it’s processing instructions in the OS To stop: AND the generator signal with 0

  20. For Monday Machine language instructions for calculations

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