The Layered Protocol Wrappers Exercise: Network Data Encryption / Decryption Using ROT13 Algorithm

1. The Layered Protocol Wrappers Exercise:Network Data Encryption / Decryption Using ROT13 Algorithm Henry Fu Washington University Applied Research Lab Supported by: NSF ANI-0096052 and Xilinx Corp. http://www.arl.wustl.edu/arl/projects/fpx/fpx_kcpsm/ hwf1@arl.wustl.edu

2. The Layered Protocol Wrappers Exercise • Network data encryption / decryption using ROT13 algorithm • Rotates characters by 13 places • ‘A’  ‘N’, ‘M’  ‘Z’, ‘a’  ‘n’, ‘m’  ‘z’ • Encryption Example: • ‘Hello World’ encrypts to ‘Uryyb Jbeyq’ • Decryption Example: • ‘Uryyb Jbeyq’ decrypts to ‘Hello World’

3. Approach to the ROT13 Algorithm • Consider the following four cases • IF (ch >= ‘A’) && (ch <= ‘M’) • Rotate “Right” ch by 13 characters • IF (ch >= ‘N’) && (ch <= ‘Z’) • Rotate “Left” ch by 13 characters • IF (ch >= ‘a’) && (ch <= ‘m’) • Rotate “Right” ch by 13 characters • IF (ch >= ‘n’) && (ch <= ‘z’) • Rotate “Left” ch by 13 characters

4. The ROT13 Module Package • The ROT13 Module Package • Detailed information on the Internet: • http://www.arl.wustl.edu/arl/projects/fpx/fpx_kcpsm/ • Download the ROT13 Module Package • Right click on ROT13.tar.gz • Save it to h:\ • Extract the ROT13 Module Package • Open a cygwin window • cd /cygdrive/h/ • gunzip ROT13.tar.gz • tar xvf ROT13.tar

5. The ROT13 Module Package (More) • The ROT13 Module Package includes • ROT13/sim/ • Modelsim simulation directory • ROT13/syn/ • Synplicity, Xinlinx backend synthesis directory • ROT13/vhdl/ • VHDL source directory • ROT13/wrappers/ • Layered Protocol Wrappers package directory

6. The ROT13 Module Framework • The ROT13 Module (“module.vhd”) is based on the ExampleApp Module • Instantiate the UDP Wrapper • Instantiate the ROT13 Application (“rot13app.vhd”) • Instantiate the UDPEcho entity • Instantiate four parallel ROT13 entity (“rot13.vhd”) • D_MOD_IN is 32-bit data bus, but we need to encrypt on a character boundary (8-bit data)

7. Overview of the ROT13 Application ROT13 Entity ROT13 Entity D_MOD_IN D_OUT_MOD 32 – Bit Data 32 – Bit Data UDPEcho Entity ROT13 Entity ROT13 Entity

8. The ROT13 Entity • The ROT13 encrypts / decrypts the characters stored in the UDP payload • Implement a state machine that steps through the ATM Cells • Looks for the start of the ATM Cell (SOF) • Looks for the start of the UDP Datagram (SOD) • Looks for the start of the UDP Payload • Encrypts the UDP Payload with the ROT13 algorithm when there are valid data • Looks for the end of the ATM Cell (EOF)

9. State Diagram of the ROT13 State Machine SOF = ‘1’ EOF = ‘1’ SOD = ‘1’ DataEn = ‘1’ IDLE REQ UDPPayload REQ2 IF DataEn = ‘1’ then Encrypts / Decrypts Payload

10. VHDL Process of the ROT13 State Machine type StateType is (Idle, Req1, Req2, UDPPayload); -- states signal state, nx_state : StateType; -- current and new state state_machine: process (Reset_l, state, sof_in, dataen_in, eof_in, sod_in, data_in) variable tmp_state : StateType; -- new state variable tmp_data : UNSIGNED (7 downto 0); begin -- process state_machine -- default value tmp_state := state; tmp_data := UNSIGNED (data_in); -- details of state machine goes here -- set state nx_state <= tmp_state; data_out <= std_logic_vector (tmp_data); dataen_out <= dataen_in; sof_out <= sof_in; eof_out <= eof_in; sod_out <= sod_in; end process state_machine;

11. Simulating the ROT13 Module • Modelsim is used to simulate the ROT13 • Go to the sim directory and create the input file • cd ROT13/sim/ • cp HELLO.DAT INPUT_CELLS.DAT • Compile the module and start Modelsim • Make compile • Make sim • In Modelsim main window, type: • do testbench.do • run 3000

12. Simulating the ROT13 Module (More) SOD indicates the start of an UDP Datagram The last two valid words are the ATM Trailer SOF indicates the start of an ATM Cell EOF indicates the end of an ATM Cell DataEn indicates the data is valid • The input data coming into the module

13. Simulating the ROT13 Module (More) The UDPPayload has been encrypted / decrypted • The output data going out of the module

14. Error Handling by the Protocol Wrappers • What happens if the incoming data is not an UDP Datagram? • If the incoming data is an ATM cell • Frame Processor drops the cell • If the incoming data is an AAL5 frame • IP Processor drops the cell • If the incoming data is an IP packet • UDP Processor does not assert the SOD signal • Application only needs to handle the last case

15. State Diagram of the New State Machine SOF = ‘1’ EOF = ‘1’ EOF = ‘1’ SOD = ‘1’ DataEn = ‘1’ IDLE REQ UDPPayload REQ2 IF DataEn = ‘1’ then Encrypts / Decrypts Payload

16. Simulating the new ROT13 • Modify the ROT13 entity to handle this case • Simulate the updated ROT13 entity • Go to the sim directory and create the IPv4 file • cd ROT13/sim/ • cp IPv4.DAT INPUT_CELLS.DAT • Compile the module in Cygwin Bash Shell • Make compile • In Modelsim main window, type: • restart -f • run 3000

17. Simulating the new ROT13 (More) SOD is not asserted between SOF and EOF • The IPv4 input data coming into the module

18. Simulating the new ROT13 (More) The IP Payload is not modified by the ROT13 entity • The IPv4 output data going out of the module

19. Synthesizing the ROT13 Module • Synplicity is used to synthesize the ROT13 • Go to the synthesis directory • cd ROT13/syn/ • Start Synplicity • make syn

20. Synthesizing the ROT13 Module (More) Files that are included in the project

21. Synthesizing the ROT13 Module (More) Click to change implementation option

22. Implementation Options for the ROT13

23. Implementation Options for the ROT13

24. Implementation Options for the ROT13

25. Implementation Options for the ROT13

26. Running the Implementation Click to run implementation

27. Synthesizing with Xilinx Backend Tools • Xilinx backend tools are used to perform backend synthesis on the ROT13 module • Go to the implementation directory • cd ROT13/syn/rad-xcve1000/ Start Xilinx backend script • ./build

28. Contents of the Xilinx Backend Script • Xilinx Backend Script • NGDBUILD • Translates and merges the various source files of a design into a single "NGD" design database. • NGD2VHDL • Translates an NGD file (NGDBUILD output) into an VHDL simulation netlist which is intended for post-synthesis simulation

29. Contents of the Xilinx Backend Script • MAP • Maps the logic gates of the NGD file (NGD output) into the CLBs and IOBs of the physical device, and writes out this physical design to an NCD file • PAR • Places and routes a design's logic components contained within an NCD file (MAP output) based on the layout and timing requirements specified within the Physical Constraints File (PCF)

30. Contents of the Xilinx Backend Script • BITGEN • Creates the configuration (BIT) file based on the contents of a physical implementation file (NCD) and defines the behavior of the programmed FPGA ngdbuild -p xcv1000e-7-fg680 rad_loopback -uc rad_loopback.ucf ngd2vhdl -w rad_loopback.ngd rad_loopback_sim.vhd map -p xcv1000e-7-fg680 -o top.ncd rad_loopback.ngd rad_loopback.pcf par -w -ol 2 top.ncd rad_loopback.ncd rad_loopback.pcf bitgen rad_loopback.ncd -b -l -w -f bitgen.ut

31. Conclusion • In this ROT13 Module Exercise • Implement a network module using the Layered Protocol Wrappers • Simulate the module using Module • Examine the generated input / output control signals and various levels of data processing • Handle special error case • Synthesize the ROT13 Module