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Asynchronous Design at CACS

Jared Tessier. Asynchronous Design at CACS. Overview. Introduction Key Async. Designs Basics Pros & Cons Performance Analysis Testing Design flow Screenshots. Introduction. Most digital circuits designed and fabricated today are “synchronous” which assume:

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Asynchronous Design at CACS

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  1. Jared Tessier Asynchronous Design at CACS

  2. Overview Introduction Key Async. Designs Basics Pros & Cons Performance Analysis Testing Design flow Screenshots

  3. Introduction Most digital circuits designed and fabricated today are “synchronous” which assume: all signals are binary all components share a common and discrete notion of time, as defined by a clock signal distributed throughout the circuit. In asynchronous circuits there is no common and discrete time. Instead the circuits use handshaking between their components in order to perform the necessary synchronization, communication, and sequencing of operations

  4. Key Asynchronous Circuit Designs ILLIAC (1952) and ILLAC2 (1962) - U. of Illinois Atlas (1962) and MU-5 (1966) - U. of Manchester Macromodules (60s-70s) - Washington U., St. Louis First commercial graphics system (70s) - Evans & Sutherland DDM dataflow computer (1978) - U. of Utah First asynchronous microprocessor (1989) - Caltech

  5. Key Asynchronous Circuit Designs First code-compatible processor (with ARM), AMULET1 (1994) - U. of Manchester Commercial pager (90s) - Phillips RAPPID (1995-9) - Intel Sensor network processor, SNAP (2004) – Cornell University @ ~24 pJ per instruction

  6. Basics – handshakes (style)

  7. Basics – handshakes (style)

  8. Basics – Muller C-element =

  9. Basics – Muller Pipeline

  10. Pros Lower system power requirements : due to fine-grain clock gating and automatic powering down of unused components. Reduced noise : local clocks tend to tick at random points in time. Average-case performance : operating speed is determined by actual local latencies rather thanglobal worst-case latency. Elimination of clock skew problems : there is no global signal that needs to be distributed with minimalphase skew across the circuit. Adaptivity to processing and environmental variations : timing is based on matched delays (and can even be insensitive tocircuit and wire delays). Component Modularity and reuse : simple handshake interfaces and local timing.

  11. Cons Greater design complexity : deadlocks, the need for mutual exclusion and arbitration, etc. Hazards : in asynchronous (control) circuits the absence of a clock means that signals are required to be valid all the time, that every signal transition has a meaning and, consequently, that hazards and races must be avoided. Lack of design tools : basically in the dark ages. Consume more area : handshaking overhead can consume more area.

  12. Performance Analysis For asynchronous design, cannot simply find critical path delay or count number of clock cycles per operation. Worst-case analysis may be quite pessimistic, as goal is to achieve high rates of performance on average. Must take a probabilistic approach to performance analysis. Most direct approach to determine performance analysis is a Monte Carlo simulation.

  13. Testing Asynchronous Circuits (the Bad) In asynchronous circuits, there is no global clock which can be used to single step the design through a sequence of steps. Asynchronous circuits have more state holding elements, which increases overhead to apply and examine test vectors.

  14. Testing Asynchronous Circuits (the Good) Since many asynchronous styles use handshakes, for many faults, a defective circuit simply halts. In the stuck-at fault model, a defect is assumed to cause a wire to become permanently stuck-at-0 or stuck-at-1. If acknowledge wire is stuck-at-0, the request is never acknowledged, causing the circuit to stop and wait forever.

  15. Our Design Flow BALSA Cadence Encounter

  16. Technology Mapping Technology mapping step takes as input a set of technology-independent logic equations and a library of cells, and it produces a netlist of cells. This has to be implemented in Balsa – so a Perl script was written to automate the task.

  17. Questions? Thanks.

  18. References D. A. Edwards, A. Bardsley, L. Janin, and W. Toms. Balsa : A Tutorial Guide. Version V3.4.2, January 2005. J. Sparso, S. Furber. “Principles of Asynchronous Circuit Design: A Systems Perspective”. Kluwer Academic Publishers, 2001. S. F. Nielsen, J. Sparso, J. Madsen. Towards behavioral synthesis of asynchronous circuits – an implementation template targeting syntax directed compilation. Proceedings of the EUROMICRO Systems on Digital System Design (DSD), pages 298–305. IEEE Computer Society Press, September 2004. Chris J. Myers. “Asynchronous Circuit Design”. Wiley, 2001. J. Pintaske. Better asynchronous than synchronous?http://www.us.design-reuse.com/articles/article5070.html V. Ekanayake, C. Kelly, R. Manohar. An Ultra Low-Power Processor for Sensor Networks. ASPLOS 2004.

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