1 / 62

Modeling of Circuits with a Regular Structure Mixing Design Styles Synthesis

ECE 448 Lecture 12. Modeling of Circuits with a Regular Structure Mixing Design Styles Synthesis. Required reading. S. Brown and Z. Vranesic , Fundamentals of Digital Logic with VHDL Design Chapter 6 .6.4 , Generate Statements Chapter A.7.5, Generate Statement

jody
Download Presentation

Modeling of Circuits with a Regular Structure Mixing Design Styles Synthesis

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. ECE 448 Lecture 12 Modeling of Circuits with a RegularStructureMixing Design StylesSynthesis ECE 448 – FPGA and ASIC Design with VHDL

  2. Required reading • S. Brown and Z. Vranesic,Fundamentals of Digital Logic with VHDL Design • Chapter 6.6.4, Generate Statements • Chapter A.7.5, Generate Statement • Chapter A.10.9, Using Subcircuits with Generic • Parameters • Chapter A.11, Common Errors in VHDL Code ECE 448 – FPGA and ASIC Design with VHDL

  3. Generate scheme for equations ECE 448 – FPGA and ASIC Design with VHDL

  4. Data-flow VHDL Major instructions Concurrent statements • concurrent signal assignment () • conditional concurrent signal assignment • (when-else) • selected concurrent signal assignment • (with-select-when) • generate scheme for equations • (for-generate) ECE 448 – FPGA and ASIC Design with VHDL

  5. For Generate Statement For - Generate label:FORidentifier IN rangeGENERATE BEGIN {Concurrent Statements} END GENERATE; ECE 448 – FPGA and ASIC Design with VHDL

  6. PARITY Example ECE 448 – FPGA and ASIC Design with VHDL

  7. PARITY: Block Diagram ECE 448 – FPGA and ASIC Design with VHDL

  8. PARITY: Entity Declaration LIBRARYieee; USEieee.std_logic_1164.all; ENTITYparityIS PORT( parity_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0); parity_out : OUT STD_LOGIC ); ENDparity; ECE 448 – FPGA and ASIC Design with VHDL

  9. PARITY: Block Diagram xor_out(1) xor_out(2) xor_out(3) xor_out(4) xor_out(5) xor_out(6) ECE 448 – FPGA and ASIC Design with VHDL

  10. PARITY: Architecture ARCHITECTUREparity_dataflowOFparityIS SIGNALxor_out: std_logic_vector (6 downto 1); BEGIN xor_out(1) <= parity_in(0) XORparity_in(1); xor_out(2) <= xor_out(1) XORparity_in(2); xor_out(3) <= xor_out(2) XORparity_in(3); xor_out(4) <= xor_out(3) XORparity_in(4); xor_out(5) <= xor_out(4) XORparity_in(5); xor_out(6) <= xor_out(5) XORparity_in(6); parity_out <= xor_out(6) XORparity_in(7); ENDparity_dataflow; ECE 448 – FPGA and ASIC Design with VHDL

  11. PARITY: Block Diagram (2) xor_out(1) xor_out(0) xor_out(2) xor_out(3) xor_out(4) xor_out(5) xor_out(6) xor_out(7) ECE 448 – FPGA and ASIC Design with VHDL

  12. PARITY: Architecture ARCHITECTUREparity_dataflowOFparityIS SIGNALxor_out: STD_LOGIC_VECTOR (7 downto 0); BEGIN xor_out(0) <= parity_in(0); xor_out(1) <= xor_out(0) XORparity_in(1); xor_out(2) <= xor_out(1) XORparity_in(2); xor_out(3) <= xor_out(2) XORparity_in(3); xor_out(4) <= xor_out(3) XORparity_in(4); xor_out(5) <= xor_out(4) XORparity_in(5); xor_out(6) <= xor_out(5) XORparity_in(6); xor_out(7) <= xor_out(6) XORparity_in(7); parity_out <= xor_out(7); ENDparity_dataflow; ECE 448 – FPGA and ASIC Design with VHDL

  13. PARITY: Architecture (2) ARCHITECTUREparity_dataflowOFparityIS SIGNALxor_out: STD_LOGIC_VECTOR (7 DOWNTO 0); BEGIN xor_out(0) <= parity_in(0); G2: FOR i IN1TO7GENERATE xor_out(i) <= xor_out(i-1) XORparity_in(i); END GENERATE G2; parity_out <= xor_out(7); ENDparity_dataflow; ECE 448 – FPGA and ASIC Design with VHDL

  14. Generate scheme for components ECE 448 – FPGA and ASIC Design with VHDL

  15. Structural VHDL Major instructions • component instantiation (port map) • component instantiation with generic • (generic map, port map) • generate scheme for component instantiations • (for-generate) ECE 448 – FPGA and ASIC Design with VHDL

  16. Example 1 ECE 448 – FPGA and ASIC Design with VHDL

  17. Example 1 s 0 s 1 w 0 w 3 s w 2 4 s 3 w 7 f w 8 w 11 w 12 w 15 ECE 448 – FPGA and ASIC Design with VHDL

  18. A 4-to-1 Multiplexer LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux4to1 IS PORT ( w0, w1, w2, w3 : IN STD_LOGIC ; s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; f : OUT STD_LOGIC ) ; END mux4to1 ; ARCHITECTURE Dataflow OF mux4to1 IS BEGIN WITH s SELECT f <= w0 WHEN "00", w1 WHEN "01", w2 WHEN "10", w3 WHEN OTHERS ; END Dataflow ; ECE 448 – FPGA and ASIC Design with VHDL

  19. Straightforward code for Example 1 LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY Example1 IS PORT ( w : IN STD_LOGIC_VECTOR(0 TO 15) ; s : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; f : OUT STD_LOGIC ) ; END Example1 ; ECE 448 – FPGA and ASIC Design with VHDL

  20. Straightforward code for Example 1 ARCHITECTURE Structure OF Example1 IS COMPONENT mux4to1 PORT ( w0, w1, w2, w3 : IN STD_LOGIC ; s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; f : OUT STD_LOGIC ) ; END COMPONENT ; SIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ; BEGIN Mux1: mux4to1 PORT MAP ( w(0), w(1), w(2), w(3), s(1 DOWNTO 0), m(0) ) ; Mux2: mux4to1 PORT MAP ( w(4), w(5), w(6), w(7), s(1 DOWNTO 0), m(1) ) ; Mux3: mux4to1 PORT MAP ( w(8), w(9), w(10), w(11), s(1 DOWNTO 0), m(2) ) ; Mux4: mux4to1 PORT MAP ( w(12), w(13), w(14), w(15), s(1 DOWNTO 0), m(3) ) ; Mux5: mux4to1 PORT MAP ( m(0), m(1), m(2), m(3), s(3 DOWNTO 2), f ) ; END Structure ; ECE 448 – FPGA and ASIC Design with VHDL

  21. Modified code for Example 1 ARCHITECTURE Structure OF Example1 IS COMPONENT mux4to1 PORT ( w0, w1, w2, w3 : IN STD_LOGIC ; s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; f : OUT STD_LOGIC ) ; END COMPONENT ; SIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ; BEGIN G1: FOR i IN 0 TO 3 GENERATE Muxes: mux4to1 PORT MAP ( w(4*i), w(4*i+1), w(4*i+2), w(4*i+3), s(1 DOWNTO 0), m(i) ) ; END GENERATE ; Mux5: mux4to1 PORT MAP ( m(0), m(1), m(2), m(3), s(3 DOWNTO 2), f ) ; END Structure ; ECE 448 – FPGA and ASIC Design with VHDL

  22. Example 2 ECE 448 – FPGA and ASIC Design with VHDL

  23. Example 2 w y w y 0 0 0 0 w y w y 1 1 1 1 y y 2 2 y y En 3 3 y w y 4 0 0 w y y 1 1 5 y y 2 6 w w y y y 2 En 0 0 3 7 w w y 3 1 1 y 2 y w w y y En En 8 0 0 3 y w y 9 1 1 y y 2 10 y y En 3 11 y w y 12 0 0 y w y 13 1 1 y y 2 14 y y En 3 15 ECE 448 – FPGA and ASIC Design with VHDL

  24. A 2-to-4 binary decoder LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY dec2to4 IS PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; En : IN STD_LOGIC ; y : OUT STD_LOGIC_VECTOR(0 TO 3) ) ; END dec2to4 ; ARCHITECTURE Dataflow OF dec2to4 IS SIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0) ; BEGIN Enw <= En & w ; WITH Enw SELECT y <= "1000" WHEN "100", "0100" WHEN "101", "0010" WHEN "110", "0001" WHEN "111", "0000" WHEN OTHERS ; END Dataflow ; ECE 448 – FPGA and ASIC Design with VHDL

  25. VHDL code for Example 2 (1) LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY dec4to16 IS PORT (w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; En : IN STD_LOGIC ; y : OUT STD_LOGIC_VECTOR(0 TO 15) ) ; END dec4to16 ; ECE 448 – FPGA and ASIC Design with VHDL

  26. VHDL code for Example 2 (2) ARCHITECTURE Structure OF dec4to16 IS COMPONENT dec2to4 PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; En : IN STD_LOGIC ; y : OUT STD_LOGIC_VECTOR(0 TO 3) ) ; END COMPONENT ; SIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ; BEGIN G1: FOR i IN 0 TO 3 GENERATE Dec_ri: dec2to4 PORT MAP ( w(1 DOWNTO 0), m(i), y(4*i TO 4*i+3) ); END GENERATE ; Dec_left: dec2to4 PORT MAP ( w(3 DOWNTO 2), En, m ) ; END Structure ; ECE 448 – FPGA and ASIC Design with VHDL

  27. Example 3 Variable Rotator ECE 448 – FPGA and ASIC Design with VHDL

  28. Example 3: Variable rotator - Interface A 16 4 B A <<< B 16 C ECE 448 – FPGA and ASIC Design with VHDL

  29. Block diagram ECE 448 – FPGA and ASIC Design with VHDL

  30. VHDL code for a 16-bit 2-to-1 Multiplexer LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux2to1_16 IS PORT ( w0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); w1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); s : IN STD_LOGIC ; f : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ) ; END mux2to1_16 ; ARCHITECTURE dataflow OF mux2to1_16 IS BEGIN f <= w0 WHEN s = '0' ELSE w1 ; END dataflow ; ECE 448 – FPGA and ASIC Design with VHDL

  31. Fixed rotation a(15) a(14) a(13) a(12) a(11) a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a(1) a(0) a(12) a(11) a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a(1) a(0) a(15) a(14) a(13) <<< 3 y <= a(12 downto 0) & a(15 downto 13); a(15) a(14) a(13) a(12) a(11) a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a(1) a(0) a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a(1) a(0) a(15) a(14) a(13) a(12) a(11) <<< 5 y <= a(10 downto 0) & a(15 downto 11); ECE 448 – FPGA and ASIC Design with VHDL

  32. Fixed rotation by L positions a(15) a(14) a(13) a(12) a(11) a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a(1) a(0) a(15-L) a(15-L-1) . . . . . . . . . . . . . . a(1) a(0) a(15) a(14) . . . . . . . a(15-L+2) a(15-L+1) <<< L y <= a(15-L downto 0) & a(15 downto 15-L+1); ECE 448 – FPGA and ASIC Design with VHDL

  33. VHDL code forfor a fixed 16-bit rotator LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY fixed_rotator_left_16 IS GENERIC ( L : INTEGER := 1); PORT ( a : IN STD_LOGIC_VECTOR(15 DOWNTO 0); y : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ) ; END fixed_rotator_left_16 ; ARCHITECTURE dataflow OF fixed_rotator_left_16 IS BEGIN y <= a(15-L downto 0) & a(15 downto 15-L+1); END dataflow ; ECE 448 – FPGA and ASIC Design with VHDL

  34. Structural VHDL code forfor a variable 16-bit rotator (1) LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY variable_rotator_16 is PORT( A : IN STD_LOGIC_VECTOR(15 downto 0); B : IN STD_LOGIC_VECTOR(3 downto 0); C : OUT STD_LOGIC_VECTOR(15 downto 0) ); END variable_rotator_16; ECE 448 – FPGA and ASIC Design with VHDL

  35. Structural VHDL code forfor a variable 16-bit rotator (2) LIBRARY ieee ; USE ieee.std_logic_1164.all ; ARCHITECTURE structural OF variable_rotator_16 IS COMPONENT mux2to1_16 PORT ( w0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); w1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); s : IN STD_LOGIC ; f : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ) ; END COMPONENT ; COMPONENT fixed_rotator_left_16 GENERIC ( L : INTEGER := 1); PORT ( a : IN STD_LOGIC_VECTOR(15 DOWNTO 0); y : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ) ; END COMPONENT ; ECE 448 – FPGA and ASIC Design with VHDL

  36. Structural VHDL code forfor a variable 16-bit rotator (3) TYPE array1 IS ARRAY (0 to 4) OF STD_LOGIC_VECTOR(15 DOWNTO 0); TYPE array2 IS ARRAY (0 to 3) OF STD_LOGIC_VECTORS(15 DOWNTO 0); SIGNAL Al : array1; SIGNAL Ar : array2; BEGIN Al(0) <= A; G: FOR i IN 0 TO 3 GENERATE ROT_I: fixed_rotator_left_16 GENERIC MAP (L => 2** i) PORT MAP ( a => Al(i) , y => Ar(i)); MUX_I: mux2to1_16 PORT MAP (w0 => Al(i), w1 => Ar(i), s => B(i), f => Al(i+1)); END GENERATE; C <= Al(4); END variable_rotator_16; ECE 448 – FPGA and ASIC Design with VHDL

  37. Constants ECE 448 – FPGA and ASIC Design with VHDL

  38. Constants Syntax: CONSTANT name : type := value; Examples: CONSTANT init_value : STD_LOGIC_VECTOR(3 downto 0) := "0100"; CONSTANT ANDA_EXT : STD_LOGIC_VECTOR(7 downto 0) := X"B4"; CONSTANT counter_width : INTEGER := 16; CONSTANT buffer_address : INTEGER := 16#FFFE#; CONSTANT clk_period : TIME := 20 ns; CONSTANT strobe_period : TIME := 333.333 ms; ECE 448 – FPGA and ASIC Design with VHDL

  39. Constants - features Constantscan be declared in a PACKAGE, ENTITY, ARCHITECTURE When declared in a PACKAGE, the constant is truly global, for the package can be used in several entities. When declared in an ARCHITECTURE, the constant is local, i.e., it is visible only within this architecture. When declared in an ENTITY declaration, the constant can be used in all architectures associated with this entity. ECE 448 – FPGA and ASIC Design with VHDL

  40. Packages ECE 448 – FPGA and ASIC Design with VHDL

  41. Explicit Component Declaration versus Package • Explicit component declaration is when you declare components in main code • When have only a few component declarations, this is fine • When have many component declarations, use packages for readability • Packages also help with portability and sharing of libraries among many users in a company • Remember, the actual instantiations always take place in main code • Only the declarations can be in main code or package ECE 448 – FPGA and ASIC Design with VHDL

  42. Explicit Component Declaration Tips • For simple projects put entity .vhd files all in same directory • Declare components in main code • If using Aldec, make sure compiler knows the correct hierarchy • From lowest to highest • Xilinx will figure out hierarchy automatically ECE 448 – FPGA and ASIC Design with VHDL

  43. METHOD #2: Package component declaration • Components declared in package • Actual instantiations and port maps always in main code ECE 448 – FPGA and ASIC Design with VHDL

  44. Packages • Instead of declaring all components can declare all components in a PACKAGE, and INCLUDE the package once • This makes the top-level entity code cleaner • It also allows that complete package to be used by another designer • A package can contain • Components • Functions, Procedures • Types, Constants ECE 448 – FPGA and ASIC Design with VHDL

  45. Package – example (1) LIBRARY ieee ; USE ieee.std_logic_1164.all ; PACKAGE GatesPkg IS COMPONENT mux2to1 PORT (w0, w1, s : IN STD_LOGIC ; f : OUT STD_LOGIC ) ; END COMPONENT ; COMPONENT priority PORT (w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; y : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ; z : OUT STD_LOGIC ) ; END COMPONENT ; ECE 448 – FPGA and ASIC Design with VHDL

  46. Package – example (2) COMPONENT dec2to4 PORT (w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; En : IN STD_LOGIC ; y : OUT STD_LOGIC_VECTOR(0 TO 3) ) ; END COMPONENT ; COMPONENT regn GENERIC ( N : INTEGER := 8 ) ; PORT ( D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; Enable, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ; END COMPONENT ; ECE 448 – FPGA and ASIC Design with VHDL

  47. Package – example (3) • constant ADDAB : std_logic_vector(3 downto 0) := "0000"; • constant ADDAM : std_logic_vector(3 downto 0) := "0001"; • constant SUBAB : std_logic_vector(3 downto 0) := "0010"; • constant SUBAM : std_logic_vector(3 downto 0) := "0011"; • constant NOTA : std_logic_vector(3 downto 0) := "0100"; • constant NOTB : std_logic_vector(3 downto 0) := "0101"; • constant NOTM : std_logic_vector(3 downto 0) := "0110"; • constant ANDAB : std_logic_vector(3 downto 0) := "0111"; • END GatesPkg; ECE 448 – FPGA and ASIC Design with VHDL

  48. Package usage (1) LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE work.GatesPkg.all; ENTITY priority_resolver1 IS PORT (r : IN STD_LOGIC_VECTOR(5 DOWNTO 0) ; s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; clk : IN STD_LOGIC; en : IN STD_LOGIC; t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ; END priority_resolver1; ARCHITECTURE structural OF priority_resolver1 IS SIGNAL p : STD_LOGIC_VECTOR (3 DOWNTO 0) ; SIGNAL q : STD_LOGIC_VECTOR (1 DOWNTO 0) ; SIGNAL z : STD_LOGIC_VECTOR (3 DOWNTO 0) ; SIGNAL ena : STD_LOGIC ; ECE 448 – FPGA and ASIC Design with VHDL

  49. BEGIN u1: mux2to1PORT MAP ( w0 => r(0) , w1 => r(1), s => s(0), f => p(0)); p(1) <= r(2); p(2) <= r(3); u2: mux2to1PORT MAP ( w0 => r(4) , w1 => r(5), s => s(1), f => p(3)); u3: priority PORT MAP ( w => p, y => q, z => ena); u4: dec2to4PORT MAP ( w => q, En => ena, y => z); u5: regn GENERIC MAP (N => 4) PORT MAP (D => z , Enable => En , Clock => Clk, Q => t ); END structural; Package usage (2) ECE 448 – FPGA and ASIC Design with VHDL

  50. Aldec Compilation Order • Include package before top-level ECE 448 – FPGA and ASIC Design with VHDL

More Related