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Instructions: Language of the Computer

Instructions: Language of the Computer. Patterson and Hennessy; Chapter 2. How is Information Stored in Memory?. Memory may be regarded as an array of storage elements, each capable of storing a single byte. 1 byte = 8 bits. Each memory element (i.e. each byte) has a unique address .

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Instructions: Language of the Computer

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  1. Instructions: Language of the Computer Patterson and Hennessy; Chapter 2

  2. How is Information Stored in Memory? • Memory may be regarded as an array of storage elements, each capable of storing a single byte. • 1 byte = 8 bits. • Each memory element (i.e. each byte) has a unique address. • Typically, information (instructions or data) is stored and exchanged as a collection of bytes called words. • 1 word = 2 – 8 bytes = 16 – 64 bits. • The length of a word is machine specific and varies from one processor to another. • The underlying hardware (e.g. buses, data ports, registers) must support the transfer of words.

  3. Assignment 1 is posted on Moodle. It is due 27-2-12 in class. Individual work.

  4. Read / Write Main Memory b Bits Chip Enable 01001101 0 11010100 1 N bits 10100010 2 Address 2N words × b bits Data : : : : b bits Data 00100001 2N-1 Address

  5. Memory Organization b-Bit Word R0 R1 b-Bit Registers Memory R2 R3 Bytes Processor MDR b-Bit Bus

  6. Memory Addresses • Every memory location is identified by a unique address. • The number of bits used to represent an address determines the size of the address space. • Assuming k address bits, it is possible to access 2k separate memory locations whose address range = 0 .. 2k - 1. • Standard memory sizes. • 1 KB = 210 bytes. • 1 MB = 220 bytes. • 1 GB = 230 bytes. • 1 TB = 240 bytes.

  7. Byte Address 8 bits Byte 0 0 1 Byte 1 2 Byte 2 Byte 3 3 2k-1 Byte 2k-1 Byte-Addressable Memory • In a byte-addressable memory, the smallest addressable unit of data is a byte. • Successive bytes are assigned successive addresses: 0, 1, 2, 3, etc… • Most computers are byte addressable.

  8. 0 1 2 3 Word-Addressable Memory • In a word-addressable memory, the smallest addressable unit of data is a word. • Word size is a machine-specific attribute. • Words are typically power-of-two multiples of bytes (e.g. 2, 4, 8, or 16 bytes corresponding to 16-, 32-, 64-, or 128-bits, respectively). Word Address Corresponding Byte Address 32 bits Word 0 0 Word 1 4 Word 2 8 Word 3 12 (2k-1)*4 2k-1 Word 2k-1

  9. 0 4 1 5 2 6 3 7 Word-Addressable Memory • Word-addressable memories are commonly built from byte-addressable memories. • 2-byte (16-bit) words are assigned addresses: 0, 2, 4, 6, 8, etc… • 4-byte (32-bit) words are assigned addresses: 0, 4, 8, 12, 16, etc… • 8-byte (64-bit) words are assigned addresses: 0, 8, 16, 24, 32, etc… Byte Address 8 bits 32-Bit Word Address Byte 0 Byte 1 Word 0 Byte 2 Byte 3 Word 1 2k-1 Byte 2k-1

  10. . . . . Byte Address Address Byte Address Address MSB LSB MSB LSB . . 0 1 2 3 0 0 3 2 1 0 4 5 6 7 4 4 7 6 5 4 2k-4 2k-3 2k-2 2k-1 2k-4 2k-4 2k-1 2k-2 2k-3 2k-4 Big Endian Addressing Little Endian Addressing Big- and Little-Endian Addressing • Big-Endian: The most-significant bytes of a word are stored in lower byte addresses. • Little-Endian: The least-significant bytes of a word are stored in lower byte addresses.

  11. Big- and Little-Endian Addressing • Example: F498B70FH • Motorola processors (e.g. MC680x0) use Big Endian addressing. • Intel processors (e.g. Pentium 4) use Little Endian addressing.

  12. Word Alignment • A word is said to be aligned if it starts at a byte address that is a multiple of the number of bytes in the word. • For a 32-bit word, aligned addresses include: 0, 4, 8, etc… • In some processors, attempting to access a non-aligned word from memory results in an error. In others, non-aligned memory accesses are acceptable.

  13. : : : : Memory Contains Machine Instructions and Data 0x0000 ADD $T0,$T1,$T2 00000001001010100100000000100000 0x0004 0x0008 -11667 11111111111111111101001001101101 0x000C ’E’’E’’C’’E’ 01000101010000110100010101000101 0xFFF8 ’3’’2’’1’ 00000000001100010011001000110011 0xFFFC

  14. Memory Map • To avoid mixing instructions, data, and restricted memory space, a memory map is defined by system designers and (typically) managed by the operating system. • The memory space is divided into regions that are each used for a dedicated purpose (e.g. storing application code, storing system code, storing static data, storing dynamic data, lookup tables, etc…). • In general, the operating system is responsible for ensuring that memory map boundaries are respected.

  15. Supporting Elementary Data Types • Numbers occupy one or more words in memory. • int sw; // single word • long int dw; // double word • Characters occupy a single byte in memory. • char c; // single byte • Strings occupy several bytes in memory. • char str[5] = {‘W’,’o’,’r’,’d’,’\0’}; // 5 bytes

  16. Main Memory MAR MDR Control R0 PC R1 ALU . . . IR SR Rn-1 Basic Processor Organization • Memory Address Register (MAR) • Stores address of next word to access from memory. • Memory Data Register (MDR) • Stores data fetched from or sent to memory. • Program Counter (PC) • Stores address of next instruction to be fetched from memory. • Instruction Register (IR) • Stores last instruction fetched from memory. • Status Register (SR) • Stores processor status information (e.g. overflow, zero, carry out, interrupt masks). LW $R0,100($R2) Processor

  17. Fetch Execute Executing a Machine Instruction LW $R0,100($R2) # $R0  Memory [100 + $R2] T1. MAR  PC; Memory Read; PC  PC + 4 T2. MDR  Memory [MAR] T3. IR  MDR T4. MAR  $R2 + 100; Memory Read T5. MDR  Memory [MAR] T6. $R0  MDR • How long does it take to fetch and execute this instruction?

  18. Instruction Set Architecture defines • The set of machine instructions that a processor can execute • The instruction set. • The number and type of operands a processor can operate on. • constants, registers, or memory addresses. • The different ways operands can be accessed. • addressing modes. • The width of the datapath. • Determines the size of elementary data types (e.g. int, double, float, etc…)

  19. Architecture vs. Organization • Computer architecture: • That part of a computer that is visible to the programmer/compiler. • Includes the set of instructions (e.g. add, multiply, and shift), addressing modes, data width, and number and types of registers. • Computer organization: • That part of a computer that is transparent to the programmer. • Includes the functional units (e.g. adders, multipliers, shifters), control mechanisms, memory hierarchy and organization, and communication mechanisms used to implement the architectural specification. • Sometimes referred to as hardware implementation or microarchitecture. • Families of computers may implement the same architecture but have different organizations (e.g. Intel 80x86).

  20. Four Categories of Machine Instructions • Machine instructions can generally be divided into four categories: • Arithmetic and logic instructions; used to process data stored (mainly) in processor registers. • Data transfer instructions; used to transfer data within the processor, or between the processor and memory. • Program sequencing and control instructions; used to transfer control from one part of a program to another; also used to test for certain conditions. • I/O transfer instructions; used to transfer data between the processor and an I/O device. In some processors, I/O transfer instructions are treated like data transfer instructions.

  21. Register operand Symbolic operand Comment Mnemonic Assembly Language Notation • Used to describe machine instructions and programs. • Instructions are described using symbolic names called mnemonics. • Operands are described using constants or symbolic names representing memory locations (i.e. memory addresses) or processor registers. • Examples: • ADDI $R4,$R0,LABEL # $R4  LABEL+$R0 • ORI $R1,$R2,255 # $R1  $R2 | 255 • SW $R5,28($R2) # Memory[28+$R2]  $R5 MIPS assembly Language

  22. Assembly Language Representations • Various forms of assembly language representations are common: • Three-address instructions. • Two-address instructions. • One-address instructions. • Zero-address instructions.

  23. Three-Address Instructions • Instructions are represented by an operation (mnemonic), two source operands, and a destination operand. • The source operands may refer to constants, memory addresses, or processor registers. • The destination operand typically refers to a processor register, but may also refer to a memory address. • Example (MIPS R2000): ADDI $R1,$R2,100 # $R1  $R2 + 100

  24. Register-Register Instruction Sets • Most modern (RISC: Reduced Instruction Set Computers) processors use three-address instruction sets where source and destination operands are commonly stored in registers. • Operands stored in registers can be accessed much faster than operands stored in memory. • Referred to as register-register instruction sets. • Example: A = B + C LW $R1,0($R4) # Assume $R4 contains &B LW $R2,0($R5) # Assume $R5 contains &C ADD $R3,$R1,$R2 # $R3  $R1 + $R2 SW $R3,0($R6) # Assume $R6 contains &A

  25. Two-Address Instructions • Instructions are represented by an operation (mnemonic), one source operand, and one destination operand. • In a two-address instruction, the destination is often an implicit source operand too. • Example (MC68000): ADD (A0),D1 ; D1  Memory[A0] + D1 • Example (Intel 80x86) ADD AX, BX ; AX  AX + BX Destination Operand

  26. One-Address Instructions • Instructions are represented by an operation (mnemonic) and a single source operand. • One-address instructions assume the presence of an implicit register called the accumulator, which is used both as a source and a destination. • Example (PIC16F84): ADDLW 100 ; W  W + 100 In the PIC16F84, the accumulator is called the working register (W).

  27. B A All operands are implicit. A TOS TOS TOS TOS TOS A + B Zero-Address Instructions • Zero-address instruction sets are used in stack-based architectures (e.g. the Java Virtual Machine – JVM). • All machine instructions operate on data stored on top of the stack (TOS). • Example: C = A + B PUSH A ;Mem[TOS]  A PUSH B ;Mem[TOS]  B ADD ;Mem[TOS]  Mem[TOS-1]+Mem[TOS] POP C ;C  Mem[TOS]

  28. Instruction Execution • All instructions are executed in two phases: • Fetch. • Execute. • Instruction fetch. • IR  Memory [PC]. • Increment PC. • Instruction execute. • Decode instruction. • Fetch operand(s). • Execute operation. • Store the result if the instruction generates one.

  29. Instruction Execution Begin execution here Address Contents # A = B + C ADDI $R4,$ZERO,B ADDI $R5,$ZERO,C ADDI $R6,$ZERO,A LW $R1,0($R4) LW $R2,0($R5) ADD $R3,$R1,$R2 SW $R3,0($R6) … .data A: .word 0 B: .word 10 C: .word 5 i LW $R1,0($R4) Program Segment for A = B + C i+4 LW $R2,0($R5) i+8 ADD $R3,$R1,$R2 SW $R3,0($R6) i+12 . . . A . . . Data for the program B . . . C

  30. Branch Instructions • Change program control flow by loading a new value in the program counter (PC). • The new address is called the branch target. • Unconditional branches • Always executed. • Example: J TARGET # PC  TARGET • Conditional branches • Executed only if a certain condition is true. Otherwise, the instruction immediately following the conditional branch is fetched next. • Example: BEQ $R1,$R2,TARGET # PC  TARGET if $R1 == $R2

  31. Branch instructions are commonly used to implement loops int sum, coeffs[100]; sum = 0; for (i = 0; i < 100; i++) { sum = sum + coeffs[i]; } To place the address of an array or a variable in a register ADDI $R1,$ZERO,coeffs # $R1  &(coeffs[0]) ADDI $R2,$ZERO,sum # $R2  &sum ADDI $R3,$ZERO,100 # $R3  100 ADD $R4,$ZERO,$ZERO # $R4  i; initialize to zero ADD $R5,$ZERO,$ZERO # $R5  temp; initialize to zero LOOP: BEQ $R3,$R4,EXIT # if (i == 100) exit the loop LW $R6,0($R1) # $R6  coeffs[i] ADD $R5,$R5,$R6 # temp  temp + coeffs[i] ADDI $R1,$R1,4 # increment $R1 ADDI $R4,$R4,1 # increment i J LOOP # goto LOOP EXIT: SW $R5,0($R2) # sum  temp

  32. Condition Codes • A collection of flags that track the results of previous instruction for use by subsequent conditional branch instructions. • Typically stored in a special condition code register or a status register. • Common condition code flags • N (negative) = 1 if result is negative; 0 otherwise. • Z (zero) = 1 if result is zero; 0 otherwise. • V (overflow) = 1 if arithmetic overflow occurs; 0 otherwise. • C (carry) = 1 if operation results in carry-out; 0 otherwise. • Branch>0 instruction tests N and Z flags. • TRUE if (N=0 AND Z=0); branch is said to be “taken”. • FALSE if (N=1 OR Z=1); branch is said to be “not taken”.

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