Programmable Elements and Their Impact on FPGA Architecture, Performance, and Radiation Hardness

1. Programmable Elements and Their Impact on FPGA Architecture, Performance, and Radiation Hardness John McCollum B0

2. Gate Array • A Gate array consists of wires and Logic Gates - typically a 2 input NAND gate. • The Key point here is UNCOMMITTED WIRING. • This takes four masks to manufacture the typical Gate Array. B0

3. Wires • Wires are very expensive and going up in price compared to logic - hence 6 layer metal. B0

4. FPGAs must add some kind of switch to the equation to be user programmable. • The size and performance of the switch essentially determines the architecture • ULM (Universal Logic Module) must be as small as possible to maximize versatility and utilization B0

5. The Switch • There are four kinds of switches • EPROM brought to us by Altera • The SRAM brought to us by Xilinx • Antifuse brought to us by Actel • Flash brought to us by Actel B0

6. Strengths Mainstream Technology Reprogrammable 100% testable non-volatile software is simple Weaknesses requires high voltage - 1 generation behind SRAM requires programmer requires socket high impedance 80uA/ minimum gate (12K ohm) impact ionization limits voltage across the device EPROM B0

7. Inversion Layer Gate Oxide Gate Source Drain n-Substrate Depletion Layer p-Substrate Back Contact Impact Ionization Electrons accelerated to 3.2eV in the high field region of the drain will enter the gate oxide conduction band B0

8. Hence PLDs • Highly efficient as a PROM • The PLD is a modification of the PROM B0

9. PLD + Wire = CPLD • CPLDs such as MAX 7000 combines PLD with PIA (Programmable Interface Array) • Hence the uncommitted wire B0

10. Programmable Interface Array • Note that the EPROM cell is used as a static pull down for a logic gate B0

11. CPLD Summary • Constant delay • Shallow logic • great for combinatorial logic , but not sequential logic • less than 5000 gates • Marginal radiation tolerance due to erasure ~20K Rads • Can suffer SEGR during programming B0

12. Strengths Base logic process - so it uses leading edge processing Re-programmable 100% testable no programmer No socket Weaknesses Largest Area element using 5 to 6 transistors plus switch = 30u2 per node @ 0.25u switch is medium impedance - 3k/ohms per square (500uA/micron) high capacitance -1.6 fA per micron/ per node @ 0.25u volatile requires external memory to load designs easily copied dead until loaded soft ware is difficult SRAM B0

13. Wires are Very Expensive • Since the switch is large and slow the module must be large so as to minimize interconnect ~ 20 gates. • The logic module must be symmetrical so all inputs are the same to minimize wires. Hence the 4X4 RAM array affectionately known as the 4 input LUT (look up table). B0

14. LUT • Add a flip flop and your done. B0

15. Altera 10K Chip B0

16. The SRAM with Lots of Metal • The SRAM FPGA has benefited the most from 5 and 6 layer metal due to the wiring complexity of flip flops. This has also altered the optimum module to 2X3 LUT and to hierarchical designs. B0

17. Actel SRAM Architecture • The Advent of 5 layer metal has made Hierarchical routing practical. B0

18. B0

19. New Module • Efficient hierarchical routing has allowed the LUT - 4 to be broken in to a 2:1 to mix of LUT 3 and LUT2. B0

20. SEU problem for SRAMS • Basically a six megabit configuration SRAM will have driver contention if a bit flips - hence the bit error rate must be in the 10-14 rate. A very difficult task. • Typical resistor approaches to harden SRAMs are in the range of 10 -10 • Still Actel is developing devices that have some level of radiation tolerance. B0

21. Highest density - a mere cross point - 10X the density of SRAM Lowest switch resistance - 25 Ohms Very low capacitance 1 fF per node.- approaching the metal line capacitance non- volatile Nearly impossible to reverse engineer Radiation hard Live with in 1 millisecond of the power supply reaching spec voltage Software is easy to place and route Antifuse Advantages B0

22. Requires programmer Requires a socket - a problem for devices with > 200 pins solved with BGA Those who design by test will throw out a lot of parts. Requires one to two transistors per wire for programming ~ 10mA for Metal antifuses. ONO antifuses require less only 5mA needed so can be programmed from the edge Some antifuse defects not testable until programming - hence only 98% to 99 % programming yield - but 100% functional Antifuse Disadvantages B0

23. Antifuse Architecture • Since wires are relatively cheap • Modules can be smaller - 3.5 real gates • Non-symmetrical hence MUX based logic • About 30 antifuses per input • Add a flip flop • Routing is very similar to Gate Array B0

24. ONO Antifuse FPGA Layout B0

25. ACT 1 MODULENote Isolation Transistor B0

26. Metal to Metal Antifuse B0

27. Sea of Modules Metal to metal antifuse moved the antifuse out of silicon making the part denser and faster B0

28. M3 M3 Antifuse M2 M2 M2 M2 M2 M2 M1 M1 M1 M1 M1 M1 M1 M1 Logic Logic Logic SRAM SRAM Logic SX Routing Efficiency • Faster Signal Propagation than SRAM FPGA • Signals travel through more interconnect in SRAM • Interconnect dominates delays in deep sub-micron • Antifuse architecture uses minimum silicon area • SRAM needs silicon overhead for interconnect B0

29. PSETB D0 DIN S1 S0 D1 Y Y D Q D2 DC IN D3 Sa Sb HCLK CLKA, CLKB DB CKS CKP CLRB A0 B0 A1 B1 A54SX Logic Element Combinatorial Cell Register Cell B0

30. SX-A = Lower Power B0

31. Antifuse Radiation • The interconnect is out of the silicon • Actel has hardened the Antifuse against SEDR • The antifuse configured MUX based logic module is not susceptible to change • The customer can make radiation tolerant flip flops out of combinatorial logic cells • Actel is hardening the Flip flop B0

32. Flash Architecture • Fundamentally similar device to EPROM but device scaling has brought a new wrinkle • since Vcc is now at 2.5 volts it is possible to use a floating gate as a switch (impact ionization) B0

33. Advantages Re-programmable in the board No socket Non-volatile One transistor instead of 6 for routing control - i.e. denser parts Passes full Vcc without pump Live at power up. Difficult to reverse engineer Disadvantages Requires high voltages About the same speed as SRAM Radiation Hardness is expected to behave similar to EPROM - has not been tested yet B0

34. SRAM based PLD FLASH based PLD Switch & Routing Memory Cell Switch & Routing Memory Cell SRAM Versus FlashSwitch & Memory Size 7 : 1 B0

35. SRAM FLASH Switch & Routing Memory Cell Switch & Routing Memory Cell ProASIC Flash Switch FLASH SWITCH WORD LINE SEL 1 SEL 2 • Smaller Die • Less Power • Non-Volatile 7 : 1 Advantage B0

36. L7 0 1 L10 F2 YL L11 I8 1 0 (long) (local) (X3) L9 L8 Pin 4 Data L4 I5 L5 (X2) L6 Pin 3 L2 L0 L13 L3 L1 L15 L12 L14 CLK I2 (X1) Pin 2 1 to 8 gates Set/Reset ProASIC Basic Logic Cell B0

37. YL F2 (local) (long) D Flip Flop D Q CLK Set L7 0 1 L10 L11 D 1 0 L9 L8 L4 CLK L5 L6 L2 L0 L13 L3 L1 L15 L12 L14 SET B0

38. Actel ProASIC 0.25µ 3LM 100K Total Gates + Memory Flash 0.2 Altera EPF10K100E 0.25µ 5LM 100K Total Gates + Memory SRAM 0.6 Relative Die Size ProASIC is 1/3 Size of SRAM FPGAs Altera EPF10K100A 0.35µ 4LM 100KTotal gates + Memory SRAM 1.0 Xilinx XC4062XL 0.35µ 3LM 5,472 LEs SRAM 1.9 Source: Xilinx Website B0

39. Flash radiation • Flash cells are usually in the 20K RAD Total Dose Range for typical 0.5u devices. • MUX based Logic can not flip • Part could be periodically refreshed to increase total dose. • Could be reconfigured in space • Programming in space can lead to SEGR - a calculated risk. B0

40. Relative Size Relative Logic Density B0

41. Relative Speed B0

42. Conclusion B0