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EuclidInside CSSE 232 Team 3-3

Learn about our microprocessor project details including instruction categories, components, testing, and lessons learned.

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EuclidInside CSSE 232 Team 3-3

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  1. EuclidInside CSSE 232 Team 3-3 Jon Gipson, Dylan Havard, Richard Hulsman, Luke May, and Richard Solotke

  2. Overview/Constraints • 16-bit Non-Proprietary Microprocessor • Input: 2 buttons & 4 Dip Switch Values • Output: 4 hex digits • Current status: Almost Working...

  3. Assembly & Machine Language • 4 Instruction Categories: • Register • add, sub, sne, slt, jr • Immediate • addi, subi, and, shift, load, store, jit, jump • Special • PUT, RFI • Pseudoinstructions • lui, clear, bne, blt

  4. Assembly & Machine Language (cont.) • 5 Instruction Types • Field Breakdown:

  5. Assembly & Machine Language (cont.) • Register type counts: • 6 Temporary Values, $at, $t0-$t4 • 3 saved values, $s0-$s2 • 2 parameters/1 return, $a0-$a1, $v0 • Dip Switch & Display, $HN, $DR • General Purpose, $ra, $0 • Interrupt Address Registers, $i0-$i2

  6. Register Transfer Language • An Example of our RTL (for store command): 0) If (IEB == 1) then 1) PC = PC + 2, IR = Mem[PC] 2) A = Reg[IR[7-4]], B = Reg[IR[3-0]] if (IR[15-12] == 1001) then 3) A = Reg[IR[7-4]], B = E[IR[3-0]] 4) SUM = A + B 5) Mem[SUM] = Reg[IR[11-8]]

  7. E.2 Datapath Components Datapath (aka Ghetto-Path) Component List: PC IPC Memory Registers Special Registers IR ALU Left Shift* Extender* A* B* C* SUM* AND* CAUSE IEB

  8. Arithmetic Logic Unit Very Simple - Performs Add/Subtract Operations Variable Barrel shifter and Variable Extender used externally to augment design. State Diagram modified to allow jumping in two directions. Outputs: Addition/Subtraction, Zero

  9. Control • 34 States for 15 Instructions, 3 Interrupts, and Display Output. • Implemented in Xilinx based on Verilog generated by StateCAD. • Most frustrating component of the project!

  10. Testing • Testing : • Sample Component Test: Register File • Test 1: Writing a value to a register and reading back from it on the next cycle. • (Hex Values) • 1st Cycle • Inputs: WD = 9999 (Data to be written) • WE = 1 (Write enable) • WriteAddr = 5 (Register to Store to) • 2nd Cycle • Inputs: RD1 = 5 (Register to Read from) • Expected output @ 2nd Cycle: RR1 = 9999 (Register output from MUX1) • Actual output: RR1 = 9999 • Analysis: The component appears to be working properly.

  11. Project Process • Stumbling points: • Group meetings • Control Unit Implementation • Interrupt Handling • “Magical” aspects at certain design steps

  12. Project Process (cont.) • Lessons learned: • Test cases • Datapath/Component Design • Xilinx Implementation • Control Unit

  13. Performance Specifications Average CPI: 5.17 cycles Clock Speed: 12.32 MHz Total Gate Count: N/A Xilinx error: IEB.ngo (CoreGEN Component) is not in .xdo format? We asked Euclid, he didn’t know either… Levels of Logic: 54

  14. Questions?

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