1 / 23

Design Optimi z ation of Mixed Time/Event - Triggered Distributed Embedded Systems

Design Optimi z ation of Mixed Time/Event - Triggered Distributed Embedded Systems. Traian Pop , Petru Eles, Zebo Peng. Embedded Systems Laboratory Computer and Information Science Dept. Linköpings universitet, Sweden. NoCs. Hard real-time constraints (e.g. X-by-wire ). Factory Systems.

jolie-gibson
Download Presentation

Design Optimi z ation of Mixed Time/Event - Triggered Distributed Embedded Systems

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Design Optimization of Mixed Time/Event-Triggered Distributed Embedded Systems Traian Pop, Petru Eles, Zebo Peng Embedded Systems LaboratoryComputer and Information Science Dept.Linköpings universitet, Sweden

  2. NoCs ... Hard real-time constraints (e.g. X-by-wire) ... Factory Systems Node 3 Node 2 Node 1 Automotive Electronics Introduction

  3. Time-Triggered (TT)Scheduling Event-Triggered (ET) Scheduling Node 3 Node 2 Node 1 CAN TTP Introduction (cont’d)

  4. Time-Triggered Functionality Event-Triggered Functionality Node 3 Node 2 Node 1 ST/DYN Bus access cycle Static (ST) communication Dynamic (DYN) communication Introduction (cont’d)

  5. Our Contribution • Design of distributed hard real-time embedded systems • Mixed ET and TT task sets • Universal Communication Model: representation of mixed ST/DYN communication protocol over the bus • Our focus: • Scheduling and timing analysis for such systems [CODES’02] • Specific design problems • Design optimization heuristic

  6. Outline • Introduction • System Model • Scheduling and Schedulability Analysis • Specific Design Problems and Design Optimization Heuristic • Conclusions

  7. I/O Node 3 Node 2 Node 1 CPU RAM ROM communication controller Tbus Tbus static phase dynamic phase dynamic phase static phase slot 2 slot 1 slot 2 slot 3 slot 1 slot 3 Hardware Architecture ST/DYN bus

  8. Application Model • Task graphs • Domains for tasks: either TT or ET • Domains for messages: either ST or DYN • Task attributes: Processor, Worst-Case Execution Time(Ci), Period, Deadline, Priority • Message attributes: Sender, Worst-Case Transmission Time, Period, Deadline, Priority

  9. Software Architecture • Real-time kernel which supports both ET and TT activities • Static cyclic scheduling for TT activities • Fixed-priority scheduling for ET activities Schedule Table Prioritized Ready List

  10. Outline • Introduction • System Model • Scheduling and Schedulability Analysis • Specific Design Problems and Design Optimization Heuristic • Conclusions

  11. OUTPUTS INPUTS Schedulability analysis Ri Di? ET tasks DYN messages Static scheduling Valid static schedule TT tasks ST messages Holistic Scheduling [CODES’2002]

  12. Outline • Introduction • System Model • Scheduling and Schedulability Analysis • Specific Design Problems and Design Optimization Heuristic • Conclusions

  13. Specific Design Problems • Partitioning of functionality into TT/ET domains • Optimization of the ST/DYN bus access cycle ST/DYN Bus access cycle

  14. Mapping Partitioning and Mapping • Partitioning of the system functionality: • Tasks:TT or ET ? • Messages: ST or DYN ?

  15. D3 D2 t1 Node1 t3 t2 Node2 t1 Node1 t3 t2 Node2 t1 Node1 t3 t2 t3 Node2 Partitioning of Functionality Node2 Node1 t2 t3 t1

  16. Static phase 2 Static phase 3 Static phase 1 Dynamic phase 1 Dynamic phase 2 Bus access cycle Optimization of Bus Access Cycle • Determining the optimal structure of the bus access cycle • Number, length and order of the ST/DYN phases

  17. t1 t1 Node1 Node1 t2 t2 Node2 Node2 Bus Bus Slot1 Slot1 Slot2 Slot2 Slot2 Slot2 DYN DYN DYN DYN Slot1 Slot1 DYN DYN DYN DYN Bus cycle Bus cycle Bus cycle Bus cycle t1 t1 Node1 Node1 t2 t2 Node2 Node2 Bus Bus Slot1 Slot1 Slot2 Slot2 Slot2 Slot2 DYN DYN DYN DYN DYN DYN Slot1 Slot1 DYN DYN Bus cycle Bus cycle Bus cycle Bus cycle t1 Node1 t2 Node2 Bus m m m m m Slot2 Slot2 DYN Slot1 DYN Slot1 Bus cycle Bus cycle Optimization of Bus Access Cycle D2

  18. Problem Definition • Input: Specification of a TT/ET Distributed Embedded System • Some tasks are not mapped • Some task graphs are not assigned to any of TT/ET domains • Output: System configuration • TT/ET partitioning • Structure of the ST/DYN Bus Cycle • Mapping of functionality on the nodes • Timing constraints of the application are satisfied

  19. Step 0: Straightforward configuration Step 1: Modify Initial Configuration Schedulable system Step 2: Mapping and Partitioning Optimization Heuristic unschedulable TT partition unschedulable ET partition Greedy assignment of tasks and messages to nodes and TT/ET domains unschedulable ET partition Exploration of various structures of the bus access cycle Step 3: Bus Access Optimization

  20. Schedulable Applications • 6 nodes • 40 applications / set • 60% processor utilisation

  21. Schedulable Applications • 60-100 tasks mapped on 4-6 nodes • 12-20 task graphs

  22. Node 3 Node 2 Node 1 Node 5 Node 4 Real-Life Example CC: 42 tasks, 11 task-graphs - 1 TT task-graph - 10 unpartitioned task-graphs - 10 unmapped tasks ABS: 35 ET tasks, already mapped Schedulable solution: 2 ET and 8 TT task-graphs

  23. Conclusions • Distributed embedded systems with mixed • TT/ET tasks sets • ST/DYN communication protocols • Specific design issues • TT/ET partitioning • Optimization of the ST/DYN Bus Cycle • Optimization Heuristic • + mapping of functionality on the nodes • + timing constraints are satisfied

More Related