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Chapter 15

WK 15. Chapter 15. PC Standard Bus Interfaces. Chapter Objectives. Describe pin and signal details of typical standard PC buses:  PCI Parallel bus  USB Serial bus Illustrate simple interfaces. The need for buses. Early PCs had a few parallel ports and serial ports

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Chapter 15

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  1. WK 15 Chapter 15 PC Standard Bus Interfaces

  2. Chapter Objectives • Describe pin and signal details of typical standard PC buses:  PCI Parallel bus  USB Serial bus • Illustrate simple interfaces

  3. The need for buses • Early PCs had a few parallel ports and serial ports • A port was needed for each device interfaced: e.g. one printer required a parallel port, e.g. COM1 • A standardbus is needed to connect several of devices (boards, equipment) made by different manufacturers

  4. Hierarchical Bus Structure of the PC Faster data transfers Plug-In Boards PCI Bus 32/64 bit data, 32/64 bit address • Faster Devices, • Larger amounts • of data Older ISA Bus 8/16 bit data, 20-bit address

  5. The PCI Parallel Bus • PCI: Peripheral Component Interconnect (1991) • Latest: PCI-Express • The only bus available as standard on current Pentium systems • 32-bit address bus (provision for 64 bits address) • Compatible with both 32-bit and 64-bit data buses • Address and data lines are MUXed to reduce size of the board edge connector • Clock speed: 33 MHz  66 MHz newer versions • The Plug & Play (PnP) Feature made it popular: Using a few registers in a small configuration EEPROM memory on the PCI board, the PC can recognize the board and configure it through software without the user setting jumpers, switches, etc.

  6. Connections on both sides PCI Pin-out (dual-in-line) • 32-bit cards (32-bit address & 32-bit data): Pins 1-62 only • 64-bit cards (64-bit address (future) & 64-bit data): Pins 1-94 Data, address 62 94

  7. PCI Burst Bus Cycle Assume 32 bit address & 32 bit data, 33 MHz clock 33 MHz Throughput  33 MHz x 4 = 132 M Byte/s Address & Data MUXed on 32 AD lines Base address 4 bytes Next 4 bytes … 1 bus cycle: transfers 16 bytes of data

  8. PCI Configuration Space Unit & Vendor IDs 2 16-bit registers Board Function, e.g. Network card, VGA card, etc. Base addresses for Both the memory and I/O spaces on the board. Codes assigned by the PCI SIG PCI board 256 Byte Configuration Memory

  9. D31-D16 of Memory Location 04H D15-D0 of Memory Location 04H

  10. The USB Bus • The universal serial bus (USB) • A very convenient way to interface many I/O device to the personal computer: keyboards, mice,flash drives, hard drives, speakers, TV tuners,webcams, etc. • The 4-wire serial bus supports multiple connected devices • Supplies power to devices

  11. The USB Bus: Some Specs • 4-wire serial bus (2 for power + 2 for signal) • Supports up to 127 device connections • Data transferred as frames (consisting of packets) using synchronous transmission: • Uses the NRZI digital code • Applies flow and error control • Implements CRC error detection • Speeds: - USB 1.1 (1994)  1.5 and 12 Mbps - USB 2.0 (2000)  Up to 480 Mbps • Cable length limits: - 3 m for full speed interface - 5 m for lower speed versions • Power provisions: 5V power supply - Low power loads: 100 mA, e.g. Keyboard - High power loads: 500 mA, e.g. hard disk

  12. The Connectors + - Serial Data + 5 V 0 V

  13. The TX/RX Interface 75773 HiZ at Receive 0 : Transmit 1 : Receive Differential (complementary) data for better immunity to noise Line Driver/Receiver IC Noise Suppression IC

  14. Data Encoding • Digital data is represented as digital signal NRZI code (but here inverts on zero) Signal is not biphase as mentioned in book Signal is unipolar (0 and +5V)

  15. NRZI encoding & Bit stuffing 0 (invert on 0) 6th 1 in a row Is replaced by 0 at TX to introduce Sync changes that keep RX synchronized to TX Process is reversed At RX to restore correct transmitted data

  16. USB Error & Flow Control 27 = 128 • Stop and Wait mechanism • (link is short!) • Data and control packets • CRC code for error detection Address Packet ID: Flag and Identifier Small CRC code for control packets Similar to ….. Frame in HDLC? Larger CRC code for data packets ACK or Negative ACK Similar to S-Frame in HDLC

  17. To serve also as a good preamble flag, it must be a unique pattern: 2nd 4 bits are complements of 1st 4 bits! (e.g. E1 = 11100001, A5 =10100101)

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