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Speed Example

Speed Example. I need the design run at 78MHZ Danny Mok Altera HK FAE (dmok@altera.com). Design Requirement. The design need to run at 78Mhz or above All the pin has been locked down, you can not changed any I/O pin

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Speed Example

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  1. Speed Example I need the design run at 78MHZ Danny Mok Altera HK FAE (dmok@altera.com)

  2. Design Requirement • The design need to run at 78Mhz or above • All the pin has been locked down, you can not changed any I/O pin • You are allowed to modify the circuit as far as the functional does not changed • You can use any design entry method • Graphic • AHDL • VHDL • anything you like

  3. Let us look at the design first All the I/O PIN can not be changed

  4. Trial Run -- What is the speed I can get God, I only get 24.63Mhz, but I need 78Mhz 78 - 24.63 = 53.37Mhz Can I make it ??????

  5. Step 1 - why it is so slow ? This is the delay path which cause it run at so slow. We must locate this path first before we can do anything

  6. Step 2 - look at the circuit The path look like this is the logic which having a large delay

  7. Step 3 - look at the module OUTPUT DEPENDS ON THE COUNTER VALUE COUNTER DFF DFF DFF Big combinational logic cause a big DELAY BEGIN IF clear='1' THEN cnt<=1; ELSE IF rowfp='1' THEN IF cnt=9 THEN cnt<=1; ELSE cnt<=cnt+1; END IF; END IF; END IF; CASE cnt IS WHEN 1 => cs<="000000001"; WHEN 2 =>cs<="000000010"; WHEN 3 =>cs<="000000100"; WHEN 4 =>cs<="000001000"; WHEN 5 =>cs<="000010000"; WHEN 6 =>cs<="000100000"; WHEN 7 =>cs<="001000000"; WHEN 8 =>cs<="010000000"; WHEN 9 =>cs<="100000000"; WHEN OTHERS =>cs<="000000000"; END CASE;

  8. Step 4 - Modify the Source Code DFF COUNTER DFF DFF DFF BEGIN IF clear='1' THEN cnt<=1; ELSE IF (rowfp'event and rowfp='1') THEN IF cnt=9 THEN cnt<=1; ELSE cnt<=cnt+1; END IF; END IF; END IF; CASE cnt IS WHEN 9 =>csnode<="000000001"; WHEN 1 =>csnode<="000000010"; WHEN 2 =>csnode<="000000100"; WHEN 3 =>csnode<="000001000"; WHEN 4 =>csnode<="000010000"; WHEN 5 =>csnode<="000100000"; WHEN 6 =>csnode<="001000000"; WHEN 7 =>csnode<="010000000"; WHEN 8 =>csnode<="100000000"; WHEN OTHERS =>csnode<="000000000"; END CASE; END PROCESS; process(rowfp,csnode) begin if (rowfp'event and rowfp='1') then cs <= csnode; end if; end process; OUTPUT DEPENDS ON THE ADVANCE COUNTER VALUE Output depends on the ADVANCE counter value Add an extra DFF

  9. Compare the Two source code BEGIN IF clear='1' THEN cnt<=1; ELSE IF (rowfp'event and rowfp='1') THEN IF cnt=9 THEN cnt<=1; ELSE cnt<=cnt+1; END IF; END IF; END IF; CASE cnt IS WHEN 9 =>csnode<="000000001"; WHEN 1 =>csnode<="000000010"; WHEN 2 =>csnode<="000000100"; WHEN 3 =>csnode<="000001000"; WHEN 4 =>csnode<="000010000"; WHEN 5 =>csnode<="000100000"; WHEN 6 =>csnode<="001000000"; WHEN 7 =>csnode<="010000000"; WHEN 8 =>csnode<="100000000"; WHEN OTHERS =>csnode<="000000000"; END CASE; END PROCESS; process(rowfp,csnode) begin if (rowfp'event and rowfp='1') then cs <= csnode; end if; end process; BEGIN IF clear='1' THEN cnt<=1; ELSE IF rowfp='1' THEN IF cnt=9 THEN cnt<=1; ELSE cnt<=cnt+1; END IF; END IF; END IF; CASE cnt IS WHEN 1 => cs<="000000001"; WHEN 2 =>cs<="000000010"; WHEN 3 =>cs<="000000100"; WHEN 4 =>cs<="000001000"; WHEN 5 =>cs<="000010000"; WHEN 6 =>cs<="000100000"; WHEN 7 =>cs<="001000000"; WHEN 8 =>cs<="010000000"; WHEN 9 =>cs<="100000000"; WHEN OTHERS =>cs<="000000000"; END CASE; Functional exactly the same

  10. Compare the stand alone module

  11. Step 5 - Recompile the design You see, so simple modification, the design performance JUMP to 73.52Mhz

  12. Step 6 - Look at the delay path again

  13. Step 7 - Which path corresponding to This is the path to cause the delay Any Suggestion ?

  14. Step 8 - Look at the source code DFF COUNTER DFF DFF IF clear='1' THEN cnt<=0;ELSE IF (clkf'EVENT AND clkf='1') THEN IF cnt=15 THEN cnt<=1; ELSE cnt<=cnt+1; END IF; END IF;END IF; IF cnt=1 THEN outv:='1';ELSE outv:='0';END IF; outb<=outv; OUTPUT DEPENDS ON THE COUNTER VALUE What is the next step ?

  15. Step 9 - Modify the source code DFF COUNTER DFF DFF DFF IF clear='1' THEN cnt<=0; ELSE IF (clkf'EVENT AND clkf='1') THEN IF cnt=15 THEN cnt<=1; outb <= '1'; ELSE cnt<=cnt+1; outb <= '0'; END IF; END IF; END IF; OUTPUT DEPENDS ON THE ADVANCE COUNTER VALUE Change the combinational logic output to DFF output by using the ADVANCE counter value

  16. Compare the Two source code IF clear='1' THEN cnt<=0;ELSE IF (clkf'EVENT AND clkf='1') THEN IF cnt=15 THEN cnt<=1; ELSE cnt<=cnt+1; END IF; END IF;END IF; IF cnt=1 THEN outv:='1';ELSE outv:='0';END IF; outb<=outv; IF clear='1' THEN cnt<=0; ELSE IF (clkf'EVENT AND clkf='1') THEN IF cnt=15 THEN cnt<=1; outb <= '1'; ELSE cnt<=cnt+1; outb <= '0'; END IF; END IF; END IF; Register output by using ADVANCE counter value Pure combinational output

  17. Compare the stand alone module

  18. Step 10 - Recompile the design again Not bad, the performance increase from 73.52Mhz to 75.18Mhz

  19. Step 11 - Locate the path

  20. The associate circuit What, this path again !!!!!!!!!!!!!!! Any Suggestion ? If can remove this AND gate ??? 13.3ns If can decrease the delay for 1ns more, then it will be good enough

  21. Are they the Same ? A A DFF C C AND DFF AND B DFF B Move the AND gate in front of the DFF !!!!!!!!!!!!

  22. Step 12 - Modify the Delay path Move the AND gate one step forward, the function is the same

  23. Step 13 - Recompile the design and Hope !! I just want 1ns, give it to me !!!! Don’t forget that we are working at 78Mhz, sometime 1ns is all what you want, but it may take you for a whole day to get it!!!!!

  24. 13 Steps change the design from 24.63Mhz to 80.64Mhz This is what Altera HK FAE can do for you

  25. Let us Review what I did • Is it always easy to modify customer design as this ? • No, if you have 1,000 line of codes, it is not easy to locate the problem, because I need to understand the design first • Do I depend on which software I use ? • No, this is design skill, not software dependent • Is it only good for Altera device ? • No, it can apply to all PLD vendors, ASIC or all design • Can not run at target performance, Engineer or Software problem ? • A good engineer knows how to increase the performance by modify his design not only blame on the software

  26. How Max+Plus II assist me in this sample ? • I use the software to help me locate the slowest path, after that, I modify the circuit • What is the different between an Engineer and a Kid ? • Those engineer does a high speed circuit design but only close his eyes and hope the software do it for him, he is not an engineer, he is a kid

  27. Engineer blame on software Engineer knows to do design • Always remember that SOFTWARE is a tools only, ENGINEER is the KEY to increase the performance

  28. Conclusion • Always, when customer have the performance problem • will contact Altera FAE • But Altera FAE is not Magician • I just spend time to locate which path is the slowest one and think how to decrease the delay • All the delay cause by : • (a) number of GATE LEVEL DELAY • (b) Routing Delay (Trace Delay) Hope this example can give you some idea how to improve performance

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