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Logic Design

Logic Design. CS 270: Mathematical Foundations of Computer Science Jeremy Johnson. Logic Design. Objective: To provide an important application of propositional logic to the design and simplification of logic circuits. 2. Topics. Logic gates a nd, or, inverter nand Logic circuits

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Logic Design

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  1. Logic Design CS 270: Mathematical Foundations of Computer Science Jeremy Johnson

  2. Logic Design • Objective: To provide an important application of propositional logic to the design and simplification of logic circuits. 2

  3. Topics • Logic gates • and, or, inverter • nand • Logic circuits • Encoder, decoder, multiplexor • Simplification of logic circuits • Full adder • Implementation of a simple processor 3

  4. Logic Circuits • A single line labeled x is a logic circuit. One end is the input and the other is the output. If A and B are logic circuits so are: • and gate • or gate • inverter (not) A B A B A 4

  5. Multi-Input Gates • Cascaded and gate • A  B  C  D  ((A  B)  C)  D  (A  B)  (C  D)  A  (B  (C  D)) A A B B C C D D A B C D 5

  6. x0 x1 s Logic Circuits • Given a boolean expression it is easy to write down the corresponding logic circuit • Here is the circuit for the original multiplexor expression 6

  7. Logic Circuits • Here is the circuit for the simplified multiplexor expression x0 x1 s 7

  8. Nand • Nand – negation of the conjunction operation: • A nand gate is an inverted and gate: x y x | y 0 0 1 0 1 1 1 0 1 1 1 0 8

  9. Implementing Logic Gates with Transistors +V +V A NAND B A output B gate ground ground A Transistor NOT Gate A Transistor NAND Gate

  10. Decoder • A decoder is a logic circuit that has n inputs (think of this as a binary number) and 2n outputs. The output corresponding to the binary input is set to 1 and all other outputs are set to 0. d0 b0 d1 b1 d2 d3 10

  11. Encoder • An encoder is the opposite of a decoder. It is a logic circuit that has 2n inputs and n outputs. The output equal to the input line (in binary) that is set to 1 is set to 1. d0 d1 b0 d2 b1 d3 11

  12. Multiplexor • A multiplexor is a switch which routes n inputs to one output. The input is selected using a decoder. d0 d1 d2 d3 s1 s0 12

  13. XOR • “One or the other, but not both” x y x  y 0 0 0 0 1 1 1 0 1 1 1 0 • Notation for circuits: x x y y

  14. Full Adder • Used to add to binary numbers stored as an array of bits using carry ripple addition • Three binary inputs • a, b and CarryIn • Two binary outputs • Sum and CarryOut such that a + b + CarryIn = 2*CarryOut + Sum Carry 110 A 101 B 111 A+B = 1100 14

  15. Exercise • Derive a truth table for the output bits (Sum and CarryOut) of a full adder. • Using the truth table derive a sum of products expression for Sum and CarryOut. Draw a circuit for these expressions. • Using properties of Boolean algebra simplify your expressions. Draw the simplified circuits. 15

  16. Building a Computer from Logic Gates • Objective: To develop a simple model of a computer and its execution that is capable of executing RAM programs. To introduce the concept of abstraction in computer design. • The model will be given schematically with timing sequences. • RAL instructions will be implemented using microinstructions described in a notation called “Register Transfer Language” (RTL). • The control logic for implementing microinstructions will be described at the gate level. References: Dewdney, The New Turing Omnibus (Chapter 48). Systems Architecture

  17. SCRAM • A Simple but Complete Random Access Machine. This computer can execute RAL instructions. • 8-bit words • 16 word memory (4 address bits) • Instructions (4 bit opcode, 4 bit operand) • 7 registers • PC (program counter) • IR (instruction register - IR(C) = instruction code, IR(O) = operand • MAR (memory address register) • MBR (memory buffer register) • AC (accumulator) • AD (register for addition internal to the ALU - arithmetic logic unit) • Driven by the CLU (control logic unit) • A timer T generates pulses that are decoded into separate input lines to the CLU Systems Architecture

  18. Fetch and Execute • A cycle of operation consists of two stages • The fetch cycle gets the next executable instruction and loads it into the IR • The execute cycle performs the instruction in the IR • The fetch and execute cycles are written as a sequence of micro-instructions described in a notation called “Register Transfer Language” (RTL) • Important: this machine uses a timer T that “ticks” several times per each of the two cycles; therefore, the fetch and execute cycles consist of several clock cycles. Systems Architecture

  19. LOAD READ/ WRITE Memory MAR LOAD PC INC MUX s 0 1 2 3 LOAD IR(C) IR(O) LOAD MUX 0 1 MBR s Decoder 0 1 2 3 MUX LOAD q9 q8 q7 q6 q5 q4 q3 q2 q1 AC x13 x12 x11 x10 x9 x8 x7 x6 x1 x2 x3 x4 x5 s MUX 0 1 ALU CLU s LOAD AD t9 t8 t7 t6 t5 t4 t3 t2 t1 t0 INC CLEAR Decoder T Systems Architecture

  20. Instruction Opcodes • LDA 0001 X; Load contents of memory address X into the AC • LDI 0010 X; Indirectlyload contents of address X into the AC • STA 0011 X; Store contents of AC at memory address X • STI 0100 X; Indirectlystore contents of AC at address X • ADD 0101 X; Add contents of address X to the AC • SUB 0110 X; Subtract contents of address X from the AC • JMP 0111 X; Jump to the instruction labeled X • JMZ 1000 X; Jump to instruction X if the AC contains 0 Systems Architecture

  21. Microprogram • Fetch cycle • t0: MAR  PC • t1: MBR  M; PC  PC + 1 • t2: IR  MBR • Execute cycle (LDA) • q1t3: MAR  IR(O) • q1t4: MBR  M • q1t5: AC  MBR Systems Architecture

  22. Microprogram • Execute cycle (LDI) • q2t3: MAR  IR(O) • q2t4: MBR  M • q2t5: MAR  MBR • q2t6: MBR  M • q2t7: AC  MBR • Execute cycle (ADD) • q5t3: MAR  IR(O) • q5t4: MBR  M • q5t5: AD  MBR • q5t6: AD  AD + AC • q5t7: AC  AD Systems Architecture

  23. Microprogram • Execute cycle (JMP) – PC relative addressing • q7t3: AC  PC • q7t4: AD  AC • q7t5: AC  IR(0) • q7t6: AD  AD + AC • q7t7: AC  AD • q7t8: PC  AC • Execute cycle (JMP) – absolute addressing • q7t3: AC  IR(0) • q7t4: PC  AC Systems Architecture

  24. Control Logic for the Fetch Cycle • t0: MAR  PC • t1: MBR  M; PC  PC + 1 • t2: IR  MBR t0 x10 x10 x4 t1 x7 x2 x5 x13 t2 x1 Systems Architecture

  25. LOAD READ/ WRITE Memory MAR LOAD PC INC MUX s 0 1 2 3 LOAD IR(C) IR(O) LOAD MUX 0 1 MBR s Decoder 0 1 2 3 MUX LOAD q9 q8 q7 q6 q5 q4 q3 q2 q1 AC x13 x12 x11 x10 x9 x8 x7 x6 x1 x2 x3 x4 x5 s MUX 0 1 ALU CLU s LOAD AD t9 t8 t7 t6 t5 t4 t3 t2 t1 t0 INC CLEAR MAR  PC Decoder T Systems Architecture

  26. LOAD READ/ WRITE Memory MAR LOAD PC INC MUX s 0 1 2 3 LOAD IR(C) IR(O) LOAD MUX 0 1 MBR s Decoder 0 1 2 3 MUX LOAD q9 q8 q7 q6 q5 q4 q3 q2 q1 AC x13 x12 x11 x10 x9 x8 x7 x6 x1 x2 x3 x4 x5 s MUX 0 1 ALU CLU s LOAD AD t9 t8 t7 t6 t5 t4 t3 t2 t1 t0 MBR  M; PC  PC + 1 INC CLEAR Decoder T Systems Architecture

  27. LOAD READ/ WRITE Memory MAR LOAD PC INC MUX s 0 1 2 3 LOAD IR(C) IR(O) LOAD MUX 0 1 MBR s Decoder 0 1 2 3 MUX LOAD q9 q8 q7 q6 q5 q4 q3 q2 q1 AC x13 x12 x11 x10 x9 x8 x7 x6 x1 x2 x3 x4 x5 s MUX 0 1 ALU CLU s LOAD AD t9 t8 t7 t6 t5 t4 t3 t2 t1 t0 INC CLEAR IR  MBR Decoder T Systems Architecture

  28. Logic for Loading the Accumulator q1 x10 t3 MAR  IR(0) x10 x4 x2 t4 x7 MBR  M x5 t5 x11 AC  MBR x11 x12 Systems Architecture

  29. LOAD READ/ WRITE Memory MAR LOAD PC INC MUX s 0 1 2 3 LOAD IR(C) IR(O) LOAD MUX 0 1 MBR s Decoder 0 1 2 3 MUX LOAD q9 q8 q7 q6 q5 q4 q3 q2 q1 AC x13 x12 x11 x10 x9 x8 x7 x6 x1 x2 x3 x4 x5 s MUX 0 1 ALU CLU s LOAD AD t9 t8 t7 t6 t5 t4 t3 t2 t1 t0 INC CLEAR MAR  IR(0) Decoder T Systems Architecture

  30. LOAD READ/ WRITE Memory MAR LOAD PC INC MUX s 0 1 2 3 LOAD IR(C) IR(O) LOAD MUX 0 1 MBR s Decoder 0 1 2 3 MUX LOAD q9 q8 q7 q6 q5 q4 q3 q2 q1 AC x13 x12 x11 x10 x9 x8 x7 x6 x1 x2 x3 x4 x5 s MUX 0 1 ALU CLU s LOAD AD t9 t8 t7 t6 t5 t4 t3 t2 t1 t0 INC CLEAR MBR  M Decoder T Systems Architecture

  31. LOAD READ/ WRITE Memory MAR LOAD PC INC MUX s 0 1 2 3 LOAD IR(C) IR(O) LOAD MUX 0 1 MBR s Decoder 0 1 2 3 MUX LOAD q9 q8 q7 q6 q5 q4 q3 q2 q1 AC x13 x12 x11 x10 x9 x8 x7 x6 x1 x2 x3 x4 x5 s MUX 0 1 ALU CLU s LOAD AD t9 t8 t7 t6 t5 t4 t3 t2 t1 t0 INC CLEAR AC  MBR Decoder T Systems Architecture

  32. CLU Logic • Some of the output lines from the two previous slides appear in both circuits. It is necessary to have some logic to connect and coordinate the individual outputs to the wires leaving the CLU. Systems Architecture

  33. Exercises • Write microprograms for STA, STI, and JMZ. Implement the microprograms in standard logic. • Design the portion of the CLU that determines the two output lines labeled x10. Input to this circuit will be one or both of the lines previously labeled x10 in the individual circuits for LDA, LDI, and the other circuits. • Convert the following program to the equivalent set of binary words, as indicated in this chapter. This is called machine code. Trace the execution of the program by listing the q, t, and x variables. • LDA 1 • ADD 2 • STA 3 Systems Architecture

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