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LOGIC DESIGN

LOGIC DESIGN. MEMORY AND PROGRAMMABLE LOGIC. EE33201 COURSE ASSESMENT MATRIX. CONVENTIONAL AND ARRAY LOGIC DIAGRAMS FOR OR GATE . BLOCK DIAGRAM OF A MEMORY UNIT . CONTENTS OF A 1024 X 16 MEMORY . Is this sequential? State diagram? Mathematical model?. CONTROL INPUTS TO MEMORY CHIP .

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LOGIC DESIGN

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  1. LOGIC DESIGN MEMORY AND PROGRAMMABLE LOGIC Ertuğrul Eriş

  2. EE33201 COURSE ASSESMENT MATRIX

  3. CONVENTIONAL AND ARRAY LOGIC DIAGRAMS FOR OR GATE Ertuğrul Eriş

  4. BLOCK DIAGRAM OF A MEMORY UNIT Ertuğrul Eriş

  5. CONTENTS OF A 1024 X 16 MEMORY Is this sequential? State diagram? Mathematical model? Ertuğrul Eriş

  6. CONTROL INPUTS TO MEMORY CHIP Ertuğrul Eriş

  7. MEMORY CYCLE TIMING WAVEFORMS Ertuğrul Eriş

  8. MEMORY CELL SRAM (Static RAM): Requires 6 transistors DRAM (Dynamic RAM): Requires a single MOS transistor and and a capacitor, Low power Ertuğrul Eriş

  9. DIAGRAM OF A 4 X 4 RAM Ertuğrul Eriş

  10. TWO-DIMENSIONAL DECODING STRUCTURE FOR A 1K-WORD MEMORY Ertuğrul Eriş

  11. ADDRESS MULTIPLEXING FOR A 64K (216) DRAM • Two dimentional Decoding: • 16 address-bit input • Address multiplexing: • 8 address-bit input • in the IC package CAS: Column Address Strobe RAS: Row Adsress Strobe • Bir önce devre ile bu devrenin karşılaştırılması: • Bacak sayısıGeçikme Ertuğrul Eriş

  12. ROM BLOCK DIAGRAM k: Number of address bits 2k: Number of address, number of n-bit-words stored 2k x n = Number of connections between AND and OR gates Ertuğrul Eriş

  13. INTERNAL LOGIC OF A 32 X 8 ROM k: Number of address bits = 5 2k: Number of address, number of n-bit-words stored = 32, n = 8 2k x n = 32 x 8 = 256 connections Ertuğrul Eriş

  14. PROGRAMMING THE ROM Ertuğrul Eriş

  15. ROM IMPLEMENTATION OF COMBINATIONAL CIRCUITS Ertuğrul Eriş

  16. BASIC CONFIGURATION OF THREE PLDs PLD: Programmable Logic Devices: Combinational, Sequentials Ertuğrul Eriş

  17. PLA WITH THREE INPUTS, FOUR PRODUCT TERMS, AND TWO OUTPUTS Ertuğrul Eriş

  18. PLA SECOND EXAMPLE F1(A, B, C) = Σ (0, 1, 2, 4) F2(A, B, C) = Σ (0, 5, 6, 7) F1 = (AB + AC+ BC)’ F2 = AB + AC+ A’B’C’ Ertuğrul Eriş

  19. PLA SIZE PROGRAMMING • n inputs, k product terms, m outputs • n buffer-inventor gates, k AND gates, m OR gates, m XOR gates • 2n x k connections between and AND array gates • k x m connections between AND and OR gates • m connections with the XOR gates • Typical: n = 16, k = 48, m = 8 • Programming • Mask programmable PLA • Field programmable PLA Ertuğrul Eriş

  20. PAL WITH FOUR INPUTS, FOUR OUTPUTS, AND A THREE-WIDE AND-OR STRUCTURE • Typical: • Four inputs, • four outputs • Four sections: • three wide AND-OR • Commercial: • eigth inputs, • eight outputs, • eigth section: • eigth-wide ABD_OR array In designing with Pal, The Boolean functions must be Simplified to fit into each section Ertuğrul Eriş

  21. FUSE MAP FOR PAL AS SPECIFIED IN THE TABLE w(A, B, C, D) = Σ (2,12,13) x(A, B, C, D) = Σ (7,8,9,10,11,12,13,14,15) y(A, B, C, D) = Σ (0,2,3,4,5,6,7,8,10,11,15) z(A, B, C, D) = Σ (1,2,8,12,13) w = ABC’ + A’B’CD’ x = A + BCD y = A’B + CD + B’D’ z = ABC’ + A’B’CD’ +AC’D’ + A’B’C’D = w + AC’D’ + A’B’C’D Ertuğrul Eriş

  22. SEQUENTIAL PROGRAMMABLE LOGIC DEVICE Ertuğrul Eriş

  23. BASIC MACROCELL LOGIC A typical SPLD 8 to 10 macrocells within one IC package OE: Output enable controls three state output buffer Ertuğrul Eriş

  24. GENERAL CPLD CONFIGURATION • (I/O) blocks provide connections to the IC pins. • Each I/O pin is driven by a three state buffer and can be programmed to act as input or output. • The switch matrix receives inputs from I/O the block and directs them to the individual macrocells. • Selected outputs from macrocells are sent to the outputs as required. • unused product terms can be used by other nearby macrocells. • PLDs sometimes called ‘function blocks’ Ertuğrul Eriş

  25. FPGA (FIELD PROGRAMMABLE GATE ARRAY) • Typical FPGA logic block consists of lockup tables, multiplexers, gates, and flip-flops. A lookup table is a truth table stored in an SRAM and provides the combinational circuit functions for the logic block. • Combinational logic section, along with a number of programmable multiplexers, is used to configure the input equations for the flip-flop and the output of the logic block. • Different firm different configurations • Requires extensive CAD tools to facilitate synthesis procedure • HDL (Hardware Description Language): ABEL, VHDL, Verilog Ertuğrul Eriş

  26. BASIC ARCHITECTURE OF XILINX SPARTAN AND PREDECESSOR DEVICES CLB: Configurable logic block IOB: Input/Output block Ertuğrul Eriş

  27. CLB(CONFIGURABLE LOGIC BLOCK) ARCHITECTURE Ertuğrul Eriş

  28. CLB ARCHITECTURE • CLB (configurable Logic Block) consists of • Look up table, muxs, registers, paths for control signals • F, G function generators • Look up tables, • generate any four varible function • H function block • Can Get its input from look up tables or from external inputs Ertuğrul Eriş

  29. CELL CONTROLLING A PIP TRANSMISSION GATE Ertuğrul Eriş

  30. CIRCUIT FOR A PROGRAMMABLE PIP Ertuğrul Eriş

  31. XC4000 SERIES IOB Ertuğrul Eriş

  32. DISTRIBUTED RAM CELL FORMED FROM A LOCKUP TABLE Ertuğrul Eriş

  33. SPARTAN DUAL-PORT RAM Ertuğrul Eriş

  34. ATRIBUTES OF THE XILINX SPARTAN XL DEVICE FAMILY Ertuğrul Eriş

  35. SPARTAN 11 DEVICE ATTRIBUTES Ertuğrul Eriş

  36. COMPARISON OF THE SPARTAN DEVICE FAMILIES Ertuğrul Eriş

  37. SPARTAN II ARCHITECTURE Ertuğrul Eriş

  38. SPARTAN 11 CLB SLICE Ertuğrul Eriş

  39. SPARTAN II IOB Ertuğrul Eriş

  40. VIRTEX II OVERALL ARCHITECTURE Ertuğrul Eriş

  41. VIRTEX IOB BLOCK Ertuğrul Eriş

  42. PROGRAM DESIGN DEPT, PROGRAM G R A D U A T E S T U D E N T STUDENT P R OG R A M O U T C O M E S PROGRAM OUTCOMES P R OG R A M O U T C O M E S STATE, ENTREPRENEUR FIELD QALIFICATIONS EU/NATIONAL QUALIFICATIONS KNOWLEDGE SKILLS COMPETENCES NEWCOMERSTUDENT ORIENTIATION GOVERNANCE Std. questionnaire ALUMNI, PARENTS ORIENTIATION STUDENT PROFILE Std. questionnaire FACULTY NGO STUDENT, ??? CIRCICULUM ??? INTRERNAL CONSTITUENT Std. questionnaire EXTRERNAL CONSTITUENT EXTRERNAL CONSTITUENT REQUIREMENTS EU/NATIONAL FIELD QUALIFICATIONS PROGRAM OUTCOMES QUESTIONNAIRES QUALITY IMP. TOOLS GOAL: NATIONAL/INTERNATIONAL ACCREDITION

  43. BLOOM’S TAXONOMYANDERSON AND KRATHWOHL (2001) !!Listening !! Doesn’t exits in the original!!! http://www.learningandteaching.info/learning/bloomtax.htm Ertuğrul Eriş

  44. ULUSAL LİSANS YETERLİLİKLER ÇERÇEVESİ BLOOMS TAXONOMY Ertuğrul Eriş

  45. COURSE ASSESMENT MATRIX LEARNING OUTCOMES Ertuğrul Eriş

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