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Trigger Board CDR

Trigger Board CDR. Matthew Warren University College London 11 October 2002. Overview. VME Module - 6U, Slave - 16 bit Data Bus (D32 okay, but only lower 16 bits data) All requirements not known - Incoming trigger unspecified - Use in ‘alien’ crates possible

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Trigger Board CDR

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  1. Trigger Board CDR Matthew Warren University College London 11 October 2002 Matthew Warren - Trigger Board CDR

  2. Overview VME Module - 6U, Slave - 16 bit Data Bus (D32 okay, but only lower 16 bits data) All requirements not known - Incoming trigger unspecified - Use in ‘alien’ crates possible - Trigger destinations unspecified (HCAL ReadOut design?) = Must have flexible I/O = Able to operate at 5V = Configurable operation - CPLD ideal Matthew Warren - Trigger Board CDR

  3. On the PCB Front-panel and Back-plane NIM/LVDS - see next slide Single, large CPLD 2 Delay-units - 64 2-5ns steps each - detect excessive Activity 50MHz Local Clock Base Address select hex-switches Super-dumb Mode jumpers - bypasses CPLD entirely Power pin select jumpers - including JAux option 8 pin Debug header for ‘scope or logic analyser Buffers for all VME signals Matthew Warren - Trigger Board CDR

  4. External I/O Front-panel NIM: 10 Inputs, 10 Outputs - Double height LEMO 00 connectors - Each signal connected to CPLD LVDS: 10x4 Fan-out - 4 IDC 20-way connectors - 10 Individual CPLD signals - Fanned-out with hardware - Custom PSU powered (only works is our crate) Back-plane LVDS: 4 Outputs - uses custom J2 pins - custom PSU powered Matthew Warren - Trigger Board CDR

  5. Generic Operation NIM - All Inputs have Outputs In-Modify-Out design Allows master-slave configuration of multiple Trigger Boards CPLD BSigOut SigIn SigOut LSigOut enSigIn VSig enSigOut VME Matthew Warren - Trigger Board CDR

  6. Firmware (or Why Use a CPLD...) VME Interface (asynchronous) VME generated Triggers etc. Status register Test registers (and stand-alone testability) Signal enables (Inputs and Outputs) Generate stand-alone 12.5MHz read-out clock Long Delays (20ns/80ns steps) Trigger-Veto-Abort cycle state-machine Activity Auto-Abort (using delay-units) Counters (Trigger number etc.) Timers Matthew Warren - Trigger Board CDR

  7. CPLD/Pins Requirements: - 167 pins + 20% margin = ~200 pins - 7ns required for 50Mhz clock - 5V Component simplifies design - Need ample logic Quickest design route – Xilinx Spartan II - Schematics for other components - Firmware too Matthew Warren - Trigger Board CDR

  8. Summary • Missing info on input/output and specific functions? • Goal is to have room for whatever is asked of us: • - Enough I/O • - Enough Pins • Enough Support Hardware Matthew Warren - Trigger Board CDR

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