Andreas Savvides andreas.savvides@yale Office: AKW 212 Tel 432-1275 Course Website

1. Sensing Platforms and Power Consumption Issues Lecture 2 September 6, 2005EENG 460a / CPSC 436 / ENAS 960 Networked Embedded Systems &Sensor Networks Andreas Savvides andreas.savvides@yale.edu Office: AKW 212 Tel 432-1275 Course Website http://www.eng.yale.edu/enalab/courses/2005f/eeng460a

2. Today • Course emphasis areas and project discussions – detailed project proposals due Sept 27 • Overview of sensing platforms • Power consumption issues

3. Need for Sensing Platforms Close coupling between fundamental research questions and the physical world In situ data collection Experimental Systems Fundamental Problems Architectural requirements • Numerous unknown factors and conditions with no prior knowledge • Sensing channels not well characterized - very complex environment • dynamics • Power consumption hard to characterize – need to understand • battery behaviors and how SW & HW components affect power • consumption

4. Some platforms & applications • Seismic monitoring, personal exploration rover, mobile micro-servers, networked info-mechanical systems, hierarchical wireless sensor networks [Intel + UCLA] [NIMS, UCLA] [Robotics, CMU] [CENS, UCLA] [Intel + UCLA] [Slide from V. Ragunanthan]

5. A Generic Sensor Network Architecture SENSING SUB-SYSTEM PROCESSING SUB-SYSTEM COMMUNICATION SUB-SYSTEM ACTUATION SUB-SYSTEM POWER MGMT. SUB-SYSTEM

6. Base Case: The Mica Mote(The most popular sensing platform today) 51-PIN I/O Connector Digital I/O Analog I/O Programming Lines AVR 128, 8-bit MCU DS2401 Unique ID Co-processor Transmission Power Control Hardware Accelerators External Flash Radio Transceiver (CC1000 or CC2420) Power Regulation MAX1678(3V) For more information refer to the TinyOS Website http://www.tinyos.net Crossbow motes at http://www.xbow.com

7. What is Stargate? • A single board, wireless-equipped computing platform • Developed at Intel Research • Leverages advances in computation, communication and storage to facilitate wireless systems research

8. System architecture

9. Computation sub-system • PXA255 processor based on the XScale microarch. • Successor to the StrongARM family • Variable clock (100 - 400 MHz), less than 500 mW power • Several sleep modes, rich set of peripherals

10. UCLA iBadge

11. Telos: New OEP Mote* • Single board philosophy • Robustness, Ease of use, Lower Cost • Integrated Humidity & Temperature sensor • First platform to use 802.15.4 • CC2420 radio, 2.4 GHz, 250 kbps (12x mica2) • 3x RX power consumption of CC1000, 1/3 turn on time • Same TX power as CC1000 • Motorola HCS08 processor • Lower power consumption, 1.8V operation,faster wakeup time • 40 MHz CPU clock, 4K RAM • Package • Integrated onboard antenna +3dBi gain • Removed 51-pin connector • Everything USB & Ethernet based • 2/3 A or 2 AA batteries • Weatherproof packaging • Support in upcoming TinyOS 1.1.3 Release • Codesigned by UC Berkeley and Intel Research • Available February from Moteiv (moteiv.com) *D. Culler, UC Berkeley

12. Wireless DPM: Hierarchical radios Mote Bluetooth IEEE 802.11 • Three vastly different wireless radios supported • Combined to form power-efficient, heterogeneous communication subsystem • Hierarchical device discovery and connection setup scheme leads to up to 40X savings in discovery power Idle current Startup time Energy per bit

13. Example Platform 1: XYZ Node Research and education node to do tasks not doable with existing nodes • Need for 32 bit computation for distributed signal processing protocols • E.g Localization protocol stacks and optimizations • Need to be closer to the Sensors • Do fast sampling and processing close to the sensors • E.g real-time acceleration or gyro measurements • Acoustic sampling and correlation – need memory, peripherals and processing to be close to the computation resource – simplifies programming • Accommodate custom form factors and interfaces for experimenting with mobile computing applications • Mobility support interfaces (stronger connectors, output for motor contollers) • Wearable applications – small package • Very low power, long term sleep modes

14. XYZ’s Architecture

15. XYZ Computation: The OKI ARM ML675001/67Q5002/67Q5003 • Features • ARM7TDMI • ROM-less (ML675001) • 256KB MCP Flash (ML67Q5002) • 512KB MCP Flash (ML67Q5003) • 8KB Unified Cache • 32KB RAM • Interrupts 25 + 1 FIQ • I2C (1-ch x master) • DMA (2-ch) • Timers (7 x 16-bit) • WDT (16-bit) • PWM (2 x 16-bit) • UART (2-ch)/ SIO (1-ch) • GPIO (5 x 8-bit) • ADC (4-ch x 10-bit) • up to 66MHz • -40 ~ +85 C • Package 144 LFBGA • 144 QFP [Slide from OKI Semiconductor]

16. OKI ARM ML675001/67Q5002/67Q5003 ARM7TDMI

17. XYZ’s Multiple Operational Modes • Sleep modes • STANDBY • Clock oscillation is stopped. • Only an external interrupt can cause CPU to exit this mode. • Wait for clock to stabilize after waking up. • HALT • Clock oscillation is not stopped. • Clock signal is blocked to specific blocks. • Any interrupt (internal or external) can cause the CPU to exit this mode • No need to wait for the clock to stabilize after waking up • Frequency scaling • 6 different operating frequencies. • 1.8MHz – 57.6MHz • Radio management • 8 discrete transmission power levels. • Sleep mode. • Turn on/off. • Individual peripherals • I/O clock is different than the CPU clock • enable/disable • internal clock divider. • Deep Sleep mode • XYZ is turned off! Only the Real Time Clock is operational. • Only the Real Time Clock can wake up the node. • Current drawn: ≈30μΑ

18. XYZ’s Deep Sleep mode: Supervisor Circuitry OKI μC 2.5V Voltage Regulator 3.3V Enable ON GPIO Interrupt (SQW) STBY INT_2 WAKEUP RTC DS1337 3 x AA batteries INT_1 I2C Step 1: Turn on the node. Step 2: The μC takes control of the Enable pin of the voltage regulator. Step 3: Turn the power switch to the STBY position. Step 4: The μC selects the total time that wants to be turned off and programs the DS1337 accordingly, through the 2-wire serial interface. Step 5: The DS1337 disables the voltage regulator and uses its own crystal to keep the notion of time. The entire sensor node is turned off! Step 6: The DS1337 enables the voltage regulator after the programmed amount of time has elapsed. Step 7: The μC takes control of the Enable pin of the voltage regulator

19. XYZ: Power Characterization Frequency Scaling • Current consumption varies from15.5mA(1.8MHz) to72mA(57.6MHz) • Disabling all the peripherals (except the timers) results to a reduction of 0.5mA (1.8MHz) to 12mA(57.6MHz) • Peripherals cause most of the overhead • SOS and Zigbee MAC layer overhead: • 2 schedulers • 4 hardware timers • 1 software timer • 20 mA @ maximum frequency

20. XYZ: Power Characterization Frequency Scaling • Current consumption varies from15.5mA(1.8MHz) to72mA(57.6MHz) • Disabling all the peripherals (except the timers) results to a reduction of 0.5mA (1.8MHz) to 12mA(57.6MHz) • Peripherals cause most of the overhead • SOS and Zigbee MAC layer overhead: • 2 schedulers • 4 hardware timers • 1 software timer • 20 mA @ maximum frequency

21. Power Mode Transitioning Overheads • Power Consumption in the HALT mode depends on the previous operating mode! • The reason is that most of the peripherals are active in the HALT mode! • Waking up the node takes orders of magnitude more time than putting it into sleep mode. This time is not software-controlled and can vary from 10 to 24ms for the maximum operating frequency. • The time that is required to wake up the processor depends on the next operating mode!

22. XYZ: Power Characterization Radio’s Power Consumption • The current drawn by the radio while listening the channel is higher than the current drawn when the radio is transmitting packets at the highest power level

23. XYZ: Software Infrastructure IEEE 802.15.4 MAC Low Power API Application Layer Dynamic Loadable Binary Modules CPU and Radio APIs Zigbee MAC protocol Operating System Hardware Drivers SOS Operating System

24. Example Platform 2: UCLA Heliomote Slide from Jonathan Friedman, UCLA, NESL

25. Heliomote Charging Circuit Slide from Jonathan Friedman, UCLA, NESL

26. Manufacturers of Sensor Nodes • Millenial Net (www.millenial.com) • iBean sensor nodes • Ember (www.ember.com) • Integrated IEEE 802.15.4 stack and radio on a single chip • Crossbow (www.xbow.com) • Mica2 mote, Micaz, Dot mote and Stargate, XSM • Intel Research • Stargate, iMote • Dust Inc • Smart Dust • Cogent Computer (www.cogcomp.com) • XYZ Node (CSB502) in collaboration with ENALAB@Yale • Mote iv – tmote sky • Sensoria Corporation (www.sensoria.com) • WINS NG Nodes • More….

27. Power PerspectiveComparison of Energy Sources With aggressive energy management, ENS might live off the environment. Source: UC Berkeley & CENS

28. Typical Operating Characteristics for 4 classes of Sensor Nodes Source: J. Hill, M. Horton, R. King and L. Krishnamurthy,”The Platforms Enabling Wireless Sensor Networks”, Communications of the ACM June 2004

29. Many ways to Optimize Power Consumption • Power aware computing • Ultra-low power design in microcontrollers • Dynamic power management HW • Dynamic voltage scaling (e.g Intel’s PXA, Transmeta’s Crusoe) • Components that switch off after some idle time • Energy aware software • Power aware OS: dim displays, sleep on idle times, power aware scheduling • Power management of radios • Sometimes listen overhead larger than transmit overhead • Modulation scaling • Apply network-wide topology management schemes • Energy aware packet forwarding • Radio automatically forwards packets at a lower level, while the rest of the node is asleep • Energy aware wireless communication • Exploit performance energy tradeoffs of the communication subsystem, better neighbor coordination, choice of modulation schemes

30. Microprocessor Power Consumption CMOS Circuits (Used in most microprocessors) Static Component Bias and leakage currents O(1mW) Dynamic Component Digital circuit switching inside the processor Dynamic Static

31. Power Consumption in Digital CMOS Circuits - current constantly drawn from the power supply - determined by fabrication technology • short circuit current due to the DC path between the • supply rails during output transitions - load capacitance at the output node - clock frequency - power supply voltage

32. Dynamic Voltage Scaling • What can you do to conserve power on a processor? • Dynamic power consumption is the dominant component • Example: Transmeta’s Crusoe processor

33. DVS on Low Power Processor Number of gates Maximum gain when voltage is lowered BUT lower voltage increases circuit delay Dynamic Power Component Load capacitance of gate k Propagation delay Transistor gain factor CMOS transistor threshold voltage

34. Voltage Scaling on LART • Dynamically lower the processor voltage and frequency to reduce power consumption • LART wearable board • StorngARM 1100 Processor 190MHz • Various I/O capabilities • 32 MB volatile memory • 4 MB non-volatile memory • Programmable voltage regulator

35. Processor Envelope At 1.5V Max clock frequency 251MHz Min frequency the processor functions correctly is 59MHz

36. LART Power Measurement Based on dhrystone benchmark • Note the measurement setup at • Different levels on the board • Always provide hooks for • measurement, testing and debugging • during your design. Both for • software and hardware!!! Total Power Consumption on the LART Platform

37. System Support Requirements • To manage DVS effectively, the computation requirements must be known in advance • Predictive scheme • Try to learn that behavior based on the computation profile • Better scheme: Applications should be power aware • Processor frequency and scaling should be changed without much delay • This is specific to each processor • 150us for the LART processor

38. Example: Power Aware Video Playback • Annotate a H.263 video decoder with information on the clock speed required to decode a known video sequence • Using a 12.6s video, 15fps • Power consumption measurements for LART • No-DVS: 198mW for CPU, 207mW for memory subsystem • DVS: 100mW for CPU and 204mW for the memory subsystem • 2X improvement, but 25% improvement when memory accesses are considered

39. LART Memory Performance • Memory access is optimal when high resolution memory access timing is available • For LART the optimal memory pattern: • 148MHz • 92 MB/s memory bandwidth • Power consumption 514.2mW • Energy cost 5.6mJ/MB

40. Power Budget Calculation Examples • Blackboard discussion • Duty cycling • Frequency scaling • Scheduling tasks tradeoffs

41. Some Platform Links Check out the IPSN 2005 program http://www.ee.ucla.edu/~mbs/ipsn05/program.html The poster and demo sessions contain links to several projects using a very wide variety of platforms