1 / 24

Dynamic Logic

Dynamic Logic. Dynamic CMOS. In static circuits at every point in time (except when switching) the output is connected to either GND or V DD via a low resistance path. fan-in of n requires 2 n ( n N-type + n P-type) devices

jthorp
Download Presentation

Dynamic Logic

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Dynamic Logic

  2. Dynamic CMOS • In static circuits at every point in time (except when switching) the output is connected to either GND or VDD via a low resistance path. • fan-in of n requires 2n (n N-type + n P-type) devices • Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. • requires on n + 2 (n+1 N-type + 1 P-type) transistors

  3. Clk Mp ((AB)+C) Out CL A C B Clk Me Dynamic Gate off Clk Mp on 1 Out In1 In2 PDN In3 Clk Me off on Two phase operation Precharge (Clk = 0) Evaluate (Clk = 1)

  4. Conditions on Output • Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation. • Inputs to the gate can make at most one transition during evaluation. • Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CL

  5. Properties of Dynamic Gates • Logic function is implemented by the PDN only • number of transistors is N + 2 (versus 2N for static complementary CMOS) • Full swing outputs (VOL = GND and VOH = VDD) • Non-ratioed - sizing of the devices does not affect the logic levels • Faster switching speeds • reduced load capacitance due to lower input capacitance (Cin) • reduced load capacitance due to smaller output loading (Cout) • no Isc, so all the current provided by PDN goes into discharging CL

  6. Properties of Dynamic Gates • Overall power dissipation usually higher than static CMOS • no static current path ever exists between VDD and GND (including Psc) • no glitching • higher transition probabilities • extra load on Clk • PDN starts to work as soon as the input signals exceed VTn, so VM, VIH and VIL equal to VTn • low noise margin (NML) • Needs a precharge/evaluate clock

  7. CL Issues in Dynamic Design 1: Charge Leakage CLK Clk Mp Out A Evaluate VOut Clk Me Precharge Leakage sources Dominant component is subthreshold current

  8. CL Solution to Charge Leakage Keeper Clk Mp Mkp A Out B Clk Me Same approach as level restorer for pass-transistor logic

  9. CL CA CB Issues in Dynamic Design 2: Charge Sharing Charge stored originally on CL is redistributed (shared) over CL and CA leading to reduced robustness Clk Mp Out A B=0 Clk Me

  10. Charge Sharing V DD M Clk p Out C L M A a X C a M = B 0 b C b M Clk e

  11. Solution to Charge Redistribution Clk Clk Mp Mkp Out A B Clk Me Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power)

  12. CL1 CL2 Issues in Dynamic Design 3: Backgate Coupling Clk Mp Out1 =1 Out2 =0 In A=0 B=0 Clk Me Dynamic NAND Static NAND

  13. Backgate Coupling Effect Out1 Voltage Clk Out2 In Time, ns

  14. CL Issues in Dynamic Design 4: Clock Feedthrough Coupling between Out and Clk input of the precharge device due to the gate to drain capacitance. So voltage of Out can rise above VDD. The fast rising (and falling edges) of the clock couple to Out. Clk Mp Out A B Clk Me

  15. Clock Feedthrough Clock feedthrough Clk Out In1 In2 In3 In & Clk Voltage In4 Out Clk Time, ns Clock feedthrough

  16. Clk In VTn Out1 V Out2 Cascading Dynamic Gates V Clk Clk Mp Mp Out2 Out1 In Clk Clk Me Me t Only 0  1 transitions allowed at inputs!

  17. Domino Logic Clk Mp Mkp Clk Mp Out1 Out2 1  1 1  0 0  0 0  1 In1 In4 PDN In2 PDN In5 In3 Clk Me Clk Me

  18. Ini Ini Ini Ini PDN PDN PDN PDN Inj Inj Inj Inj Why Domino? Clk Clk Like falling dominos!

  19. Properties of Domino Logic • Only non-inverting logic can be implemented • Very high speed • static inverter can be skewed, only L-H transition • Input capacitance reduced – smaller logical effort

  20. Designing with Domino Logic V V DD DD V DD Clk M Clk M p p M r Out1 Out2 In 1 PDN In PDN In 2 4 In 3 Can be eliminated! M Clk M Clk e e Inputs = 0 during precharge

  21. Footless Domino The first gate in the chain needs a foot switchPrecharge is rippling – short-circuit current A solution is to delay the clock for each stage

  22. Differential (Dual Rail) Domino off on Clk Clk Mp Mkp Mkp Mp Out = AB Out = AB 1 0 1 0 A !A !B B Clk Me Solves the problem of non-inverting logic

  23. np-CMOS Clk Me Clk Mp Out1 1  1 1  0 In4 PUN In1 In5 In2 PDN 0  0 0  1 In3 Out2 (to PDN) Clk Mp Clk Me Only 0  1 transitions allowed at inputs of PDN Only 1  0 transitions allowed at inputs of PUN

  24. NORA Logic Clk Me Clk Mp Out1 1  1 1  0 In4 PUN In1 In5 In2 PDN 0  0 0  1 In3 Out2 (to PDN) Clk Mp Clk Me to other PDN’s to other PUN’s WARNING: Very sensitive to noise!

More Related