3D Design Flow @ IPHC

1. 3D Design Flow @ IPHC Frédéric Morel - Grégory Bertolone - Claude Colledani

2. Standard and IO cells (1) • Building DfII libraries for ARM cells • symbols and cmos_sch views: use directly the dfII files • layout view: import of the gds file • Use of the metal 5 top for IO cells (for having large VIA4 and no MET6) • verilog view: import and compile the verilog file • vhdl file is available but not used • schematic view: import of the cdl netlist • Use a skill function for changing VSS and VDD to VSS! and VDD! • Device mapping between the devices of cdl netlist and Chartered DfII library (chrt013lp) • transistors and resistors, no diode was imported • abstract view: import of the lef file • Change the lef file for metals and vias • METALx  METx, VIAxy  VIAx, and VIAxy_H/V  Mx_My • By default layers used in abstract are invisible (LSW) 3D workshops (Marseille) frederic.morel@ires.in2p3.fr

3. Standard and IO cells (2) • Test of the DfII ARM libraries against CAD tools • Simulations • Analogue (spectre), mixte (ams) and digital (nc-verilog) • Synthesis, place & route, timing analysis and post-simulations • tlf files exist to perform timing analysis • RTL compiler, SOC • Post-simulations and post-timing analysis (need handmade modifications, should be solved) • DRC and LVS • These libraries are fully compatible within DfII • Available for others users (NDA signed) 3D workshops (Marseille) frederic.morel@ires.in2p3.fr

4. Extraction • Extraction made with Calibre and Hercules/STAR • Extraction with both tools have similar results • Modification of the original scripts necessary for creating a dspf extracted netlist • Simulations with spectre and ams in DfII • Use directly this netlist with a config view • Does not work each time (complexity of the extracted cell) • Import like a cdl netlist for generating a schematic • Need to modify the original netlist • PININFO are not present • Modifications are handmade but a script can be developed • Need to create a device map file • For mapping cdl netlist devices and Chartered devices (Transistors, parasitic and physical resistors and capacitors) • Once for the kit (not tested with physical resistors and capacitors) • Future plans for a robust extraction flow? 3D workshops (Marseille) frederic.morel@ires.in2p3.fr

5. Scripts (1) • MIM capacitances for Calibre LVS • With 2 top metals options 2 types of MIM cap are available • For 6 metals layers: METTOP/MET5 and MET5/MET4 • Only MIM cap between METTOP/MET5 are extracted • Modification of the Calibre LVS extract rules • Extraction of MIM devices between METTOP/MET5 • If 2 top metals options is not set • Default rules • Extraction of MIM devices between MET5/MET4 • If 2 top metals options is set • METTOP/MET5 MIM cap are not extracted • Calibre DRC rules take into accounts both types of MIM cap • Are really two types of MIM caps available? 3D workshops (Marseille) frederic.morel@ires.in2p3.fr

6. Scripts (2) • Verifications of connections between metal 6 BI • Assura DRC LvL of 2 tiers with specific rules • Check that all BIs are face to face in each tier • Check that BIs with the same label name are face to face in each tier • Check that BIs which enclose VIATOP are face to face in each tier • LvL must be done before the mirroring of the second tier BI Label1 Label2 VIATOP 3D workshops (Marseille) frederic.morel@ires.in2p3.fr

7. Lb<1> Lb<2> Lb<3> Lb<4> Lb<5> Lb<6> Scripts (3) • Array of labels generator • Arrays of pixels need 1-dim. vectorized labels • Pix(x,y) Label<v> • To perform a LVS • To check connectivity between both tiers • This script allows us to create bus labels • Labels are place as an array • different size of rows and columns • different horizontal and vertical pitches • Fully customizable • In Cadence 5.1.41 pin vector limit is set to 64k in schematic view • Check and save is very slow • cdl export is also very slow Lb<11> Lb<7> Lb<3> Lb<9> Lb<5> Lb<1> 3D workshops (Marseille) frederic.morel@ires.in2p3.fr

8. Scripts (4) • Check shapes in METx label • In Calibre METx drawing, dummy and label are extracted as nets • In the manufacturing stream layer table METx labels are not exported • By default the display are the same for all of theses subtypes • We create a Calibre rules to check if METx labels are used to create shapes • Shapes_label.Metalx{@ Shapes in Metal x COPY Metalx_Label} • Dummy Filling • The filling in this technology is not obvious • We use the CMP filling script (with Assura) 3D workshops (Marseille) frederic.morel@ires.in2p3.fr

9. Miscellaneous (1) • Stream Layer Map Table • Some marking layers are defined in marking and drawing with the same gds subtype • LVS_PSUB2, SRAMCORE, DIODE_MK, … • Not easy to verify LVS and DRC in the import gds file • Source of mistakes ? • AMS simulations • By default models are not load when ams simulator is chosen • libInitCustomExit.il file must be updated with the right path • Some models files must be also updated (syntax problems) 3D workshops (Marseille) frederic.morel@ires.in2p3.fr

10. Miscellaneous (2) • Chip ID block • Placement understanding of the chip ID has been different from labs to labs • Should we have to clarify this point? • Mailing at IPHC • For a better diffusion of information we have a new mailing list 3DIC@iphc.cnrs.fr • People in this list • G. Bertolone, G. Claus, C. Colledani, W. Dulinski, Y. Fu, C. Hu, F. Morel, O. Torheim, X. Wei and M. Winter • The management of the list is transparent for users • Please use it 3D workshops (Marseille) frederic.morel@ires.in2p3.fr

11. Kit version • Issues with Chartered/Tezzaron kit versions • The first kit version has a conflict between Tezzaron and Chartered • Both tech file containing identical layer info • Tezzaron rules have changed during the design • DRC with different rules release in IPHC and FNAL • Chartered kit configuration is complex • There is a lot of options for DRC and LVS • Options for setting the right process • Options for setting the checks for the DRC • An official procedure for verifying the version of the rules, the right options set up is necessary 3D workshops (Marseille) frederic.morel@ires.in2p3.fr

12. Suggestions • How can we have a homogeneous CAD flow? • Same for standard and IO cells? • With Synthesis, Place and Route, pre- and post- timing analysis • Example of CERN with IBM flow? 3D workshops (Marseille) frederic.morel@ires.in2p3.fr