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A Faster Satisfiability Model and Algorithm for Circuit Delay Computation

鍾逸亭. A Faster Satisfiability Model and Algorithm for Circuit Delay Computation. Outline. Model introduction Arrival time information Example Modified arrival time Comparasion with papers Future work. Model introduction (1/2). Floating mode sensitization

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A Faster Satisfiability Model and Algorithm for Circuit Delay Computation

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  1. 鍾逸亭 A Faster Satisfiability Model and Algorithm for Circuit Delay Computation

  2. Outline • Model introduction • Arrival time information • Example • Modified arrival time • Comparasion with papers • Future work

  3. Model introduction (1/2) • Floating mode sensitization • On-input can decide the final value of the gate. • On-input is the earliest controlling-value, or • On-input is the latest nc and side-inputs are nc. • Viability mode sensitization • If a gate is stable no earlier than t (arrival ≧ t), • At least a fanin is stable no earlier than t-d, and • Either a fanin is stable no earlier than t-d or is nc. • Two model have the same delay • Viability model has a simpler format On-input of AND = Earliest 0, or Latest 1, other are 1 0 0 0 1 1 0 1 1

  4. Model introduction (2/2) • Viability model for circuit delay computation • We want to check whether circuit delay ≧ D • X is the TCF, X(p,D)=1 means arrival(p) ≧ D • For a X, it can be compute recursively 3(2+k) clauses • In fact, we only need to build the positive X model: 1+k clauses Ex. Check D=2 p a b g

  5. Arrival time information Arrival = 4, 6 X≦4 = 1  Arrival must ≧ 4 X5 = X6 Arrival ≧ 5 means Arrival ≧ 6 X>6 = 0  Arrival cannot > 6 4 2 X( f, t)= 1 X(f,t2) X(f,t3) … 0 2 arrival t1 t2 t3tmax

  6. Example 1. Compute all arrival time 2. Construct TCF model for max delay=7 3. Apply SAT solver to make some XPO=1 #TCF = 4 X( f, t)= 1 X(f,t2) X(f,t3) … 0 4,5,6,7 2 2 1 1 1 3 4,5 X4=0 X4 X6=0 X6 0 0 A B X7 X3=1 X3=0 X5 X5=0 arrival t1 t2 t3tmax 3,4 3,5,6

  7. Example 1. Compute all arrival time 2. Construct TCF model for max delay=7 Reduce max delay 3. Apply SAT solver to make some XPO=1 0 0 A B X7 =1 X4 =1 1 X5 =1 X6 =1 1 0 Conflict! 1 1 1 1

  8. Example 1. Compute all arrival time 2. Construct TCF model for max delay=6 3. Apply SAT solver to make some XPO=1 #TCF = 4 X( f, t)= 1 X(f,t2) X(f,t3) … 0 Two cases 4,5,6,7 2 2 1 1 1 3 4,5 X4=0 X4 X5 X5 0 0 A B X6 X3=1 X3=0 X4=1 X4=0 arrival t1 t2 t3tmax 3,4 3,5,6

  9. Example 1. Compute all arrival time 2. Construct TCF model for max delay=6 3. Apply SAT solver to make some XPO=1 Case1: 0 =1 X5 A B X6 =1 1 0 X4 =1 1 0 Conflict! 1 1 1

  10. Example 1. Compute all arrival time 2. Construct TCF model for max delay=6 Reduce max delay 3. Apply SAT solver to make some XPO=1 Case2: 0 X5 A B X6 =1 =1 1 1 0 Conflict! 1 1 1

  11. Example 1. Compute all arrival time 2. Construct TCF model for max delay=5 3. Apply SAT solver to make some XPO=1 #TCF = 2 X( f, t)= 1 X(f,t2) X(f,t3) … 0 4,5,6,7 2 2 1 1 1 3 4,5 X4=1 X4 0 0 A B X5 X3=1 X3=0 arrival t1 t2 t3tmax 3,4 3,5,6

  12. Example 1. Compute all arrival time 2. Construct TCF model for max delay=5 3. Apply SAT solver to make some XPO=1 Total # TCF = 10 X( f, t)= 1 X(f,t2) X(f,t3) … 0 4. True delay = 5 1 X4 A B X5 =1 =1 or0 1 1 0 arrival t1 t2 t3tmax 0 SAT!

  13. Modified arrival time There may be some false arrival time in the circuit. (Unit arrival time must be true, so we need not to check) We can pick a cut of circuit and check the critical arrival time. Then we can propagate new arrival time information to PO. If X(PO, max delay) is UNSAT, repeat 2. True arrival time X4=1 X4=0 4, 5, 6, 7 2 1 1 1 3 4, 5 0 0 A B X5 1 0 0 3, 4 3, 5, 6 UNSAT UNSAT 0 2 SAT! Total # TCF is reduced form 10 to 3.

  14. Modified arrival time • Cut Strategy: • Critical arrival time number <= cutLimit • Start from the level_num*ratio level • Offset

  15. Comparasion with papers • Model • floating-mode sensitization • # TCF vars • Run time

  16. Model-formulae

  17. Model-cnf K-input gate

  18. Model-circuit delay

  19. # Variables

  20. Run time of SAT solver

  21. Future Work How to find a better cut or … Find all true paths with delay >= D. Extend unit delay model to continuous model. Timing optimization needs what information?

  22. Reference [1] Satisfiability Models and Algorithms for Circuit Delay Computation. Luís Guerra e Silva, João P. Marques Silva, Luís Miguel Silveira and Karem A. Sakallah. Cadence European Laboratories [2] Efficient Boolean Characteristic Function for Timed Automatic Test Pattern Generation. Yu-Min Kuo, Student Member, IEEE, Yue-Lung Chang, and Shih-Chieh Chang, Member, IEEE

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