Accellera Technical Activities General Overview

1. Accellera Technical ActivitiesGeneral Overview July 26, 2006 Accellera Membership Meeting Johny Srouji & TC Chairs

2. Outline • Overall TC Structure & Activities • Deeper dive into four activities: • SystemVerilog • OCI • VHDL • OVL

3. TCC Chair Johny Srouji AMS Sri Chandra OVL Mike Turpin Interfaces (ITC) Brian Baily OCI Bruce Cory VHDL Lance Thompson P1800 SystemVerilog Johny Srouji P1850 PSL Harry Foster Accellera TC Structure Admin Assistance – Lynn Horobin

4. 2003 2004 2005 2006 2007 SystemVerilog 3.1 3.1a IEEE 1800 1800.V07 OVL Verilog/SVA PSL VHDL SystemC • OVL 1.0 OVL 1.9 OVL 2.0 • Kicked off • Kicked off VHDL VHDL 1.0 VHDL 3.0 VHPI 2.4 OCI OCI 1.0 OCI 1.0 Verilog-AMS 2.1 • 2.2 • Compact Device Model 2.3 Verilog-2005-AMS 3.0 SystemVerilog-AMS ITC (SCE-API) 1.0 1.1 1.6 .. 1.9 1850.V07 PSL 1.01 1.1 IEEE 1850 Overall Activities

5. SystemVerilog Johny Srouji

6. SystemVerilog 3.0 Accellera Extensions to V2K SystemVerilog 3.1a Accellera Extensions to 3.1 2001 2002 2003 SystemVerilog 3.1 Accellera Extensions to 3.0 SystemVerilog 3.1a transfer to IEEE P1800 Verilog-2001 (V2K) Enhancement – 2nd IEEE Verilog Standard SystemVerilog History Oct’2004 2004 SystemVerilog IEEE 1800 Standard was Approved in November 2005

7. Verilog Testbench DPI & API Interface SystemVerilog Components Advanced verification capability for semiformal and formal methods. The Assertion Language Standard for Verilog Transaction-Level Full Testbench Language with Coverage Verilog Testbench Verilog Assertion IEEE Verilog 2005 Verilog Design Design Abstraction: Interface semantics, abstract data types, abstract operators and expressions Direct C interface, Assertion API and Coverage API

8. SystemVerilog Overview • Leverages verification features: OO and unsized data types • Classes, queues, strings, dynamic arrays, associative arrays • Code functionality more abstractly as in C/C++ • Refine design through levels of abstraction • Enablement of verification as an integral part of the design language • Same language for abstract and detailed modeling of the design, Assertions and Test Bench • Enablement of design Abstraction - high impact on productivity • Concise capturing of designer intent • Better consistency between synthesis and simulation • C language semantics and data types, communication interfaces • Easy integration to external drivers implemented using a different language (e.g. C/C++) • Wide usage and support by the EDA

9. IEEE P1800 SystemVerilog WG P1800 Errata Sub-WG SV-BC SV-EC SV-AC SV-CC Organization IEEE P1800 Structure Chair - Johny Srouji Vice chair – Shrenik Mehta Secretary - Dennis Brophy IEEE 1364 Features are now driven by the IEEE 1800 technical committees: • Language issues in SV-BC • C-Interface issues in SV-CC Chair: Karen Pieper Champions

10. Large Industry Contributions

11. VhdlCohen Training Broad Industry Support CBE WSFDB Consulting

12. P1800 Goals - The Big Picture • Develop, Approve and Publish an IEEE standard of SystemVerilog 1800 and Verilog 1364 • New PAR (Project Authorization Request) was prepared and submitted to NESCOM • Next revision targeted for submission to the IEEE in December of 2008 • Merge IEEE 1364 Verilog standard into P1800 SV Standard • Add clarifications and correct errata • Local enhancements to ensure successful use • Enhancements to SVA • Enable interoperability with other standards • VHDL, AMS, SystemC, etc • Plan to maintain a “live” version of the LRM

13. IEEE 1800-2005 SystemVerilog • IEEE 1800-2005 Standard for SystemVerilog : Unified Hardware Design, Specification and Verification Language • Can be purchased from http://shop.ieee.org/ieeestore/ • Pricing Information: • IEEE Product No.: SS95376 • List Price: $55.00 • IEEE Member Price: $45.00 • ISBN: 0-7381-4811-3 • IEEE Standard No.: 1800-2005

14. Contacts & Participation • IEEE meetings are open to the public • Everyone is welcome to attend meetings and voice their opinions • Voting membership / balloting • By company, requires IEEE-SA membership • Working Group: • Web site: http://www.eda.org/sv-ieee1800/ • Chair: Srouji@US.IBM.com • Vice Chair: Shrenik.Mehta@sun.com • Secretary: dennisb@model.com

15. Open Compression Interface(OCI) Bruce Cory

16. Why OCI? • Current on-chip scan compression flows use proprietary solutions that require same vendor tools for test logic insertion, pattern generation, and diagnosis. • This limits a users ability to choose the best fit tools for pattern generation and diagnosis • The situation is particularly restrictive in cases where multiple foundries or cores are used and each supports different compression solutions • It also limits vendor ability to compete for a user’s business

17. OCI Mission & Scope • Mission: • Develop an Open Compression Interface to on-chip scan compression structures such that EDA tools may interoperate between different compression architectures for pattern generation and diagnosis • Scope: • Define extensions to CTL to describe the behavior of on-chip test compression structures

18. OCI Roster’s list

19. OCI Clarifications • This is not a standardization of the compression algorithms or architectures. • OCI will not have any impact on the architecture or implementation of compression structures • OCI will support representation of most types of compression structures. • Only current limitation is support of compression structures where the internal scan chains dynamically change length from pattern to pattern. • OCI is not meant to replace how information is passed for same vendor tool flows. • OCI description of compression structures does not guarantee vendor interoperability. • Vendor support will be up to each individual vendor company

20. What Happened in the Last Year • Held 30 phone conferences and 1 face to face • Active team members include Cadence, Synopsys, Mentor Graphics, Intel, NVIDIA, and more • Developed and documented OCI syntax and semantics to support most vendor structures • Only LogicVision structure not currently supported • Due to per pattern changing mapping of scan in data to flops • Documented five examples which validate the OCI description for most widely used compression structures • Balloted in the OCI technical sub-committee to pass the standard on 7/18/2006 • Unanimous vote to pass

21. Plans for the Rest of the Year • Pass balloting at the Accellera technical committee and board of directors level • Goal is to achieve by early September • Work with IEEE to pass the standard as an IEEE1450.n STIL standard extension

22. VHDL Lance Thompson

23. VHDL – Charter & Overview • Define and deliver, in form of a draft LRM, enhancements to IEEE Standard VHDL 1076. • Objectives • Maintain the precision and depth of thought that has been applied to VHDL over the years • Prioritize and identify language features that VHDL users deem valuable and of high priority. • Leverage existing work in from the "Fast Track" group that exists under the IEEE. • Incorporate IEEE VASG resolutions to all known issues and issues found from implementation by vendors and customer usage. • Process any donations or proposals that are made according to the defined process. • Complete 2006 release of the Accellera Standard VHDL Language Reference Manual by DAC 2006 for donation back to the IEEE. • Continue work on future releases of the Accellera Standard VHDL and donating them to the IEEE

24. VHDL – Status • Draft 2.4c • VHPI • Accellera approved • Released to IEEE • Draft 3.0 • Lots of Stuff • Accellera votes today

25. VHDL - structure “Users” ISAC • Chair – Lance Thompson • Vice-chair – John Ries • User and Vendor representation • 10 Member Companies • 60 Technical members Requirements SC Jim Lewis Extensions SC Ajay Varikat Review SC Lance Thompson LRM SC Lance Thompson LRM

26. VHDL Roster’s list

27. VHDL – 2006 milestones

28. VHDL – 2006 milestones

29. VHDL – Plans (H2’06 and 2007) • Support 2.4c through IEEE process • Technical editing • Support Trial Implementations of 3.0 • LRM SC to act like an ISAC • Develop further extensions • Object Orientation • Constrained Random • Complex “interfaces” • Others selected by the Requirements SC

30. Open Verification Library(OVL) Mike Turpin / Kenneth E. Larsen

32. Agenda • Charter of OVL • Goal and objectives • Committee structure • Plan • Schedule • Milestones • Issues / Risk / Other

33. Charter of OVL • “Define and deliver Accellera Standard OVL LRM and libraries of assertion checkers to be used by design, integration and verification engineers to check for good/bad behavior in simulation, emulation and formal verification – provided in Verilog, System Verilog, VHDL, PSL, and SystemC”

34. Goals and objectives • Resolve all known issues and issues found from implementation by vendors and customer usage • Process any donations or proposals that are made according to the defined process • Complete V1.7 release of the Accellera Standard OVL libraries and Library Reference Manual (LRM) by DAC 2006 • Continued work on future releases of the Accellera Standard OVL libraries

35. Community structure • OVL committee restructured into one committee • Chair: Mike Turpin / ARM • Co-Chair: Kenneth Larsen / Mentor Graphics • Technical overview: Harry Foster / Mentor Graphics • Restructure in effect per 1. January 06 • Communicated to committee 30. Nov 05 • General support of change

36. Schedule • Major: Accellera Standard OVL release • Minor: Accellera OVL committee patch release

37. 2006 Milestones • Milestones to meet up to Version 1.7 release: • DVCon, 22nd-24th Feb 2006, San Jose - DONE • 2 papers accepted on OVL, and PFV including OVL • DATE, 6th-10th March 2006, Munich - DONE • OVL user event • DAC, 24th-28th July 2006, San Francisco • Accellera Standard OVL V1.7 • OVL user event (Marriot Hotel, Wed 26th 1:30pm – 3:30pm) • OVL Birds-of-a-Feather meeting

38. Donations & IP • Donations • Accepted Intel donation of the specification of 11 liveness checkers to be used with Formal Verification • Accepted Synopsys donation of 20 SV checkers for review • By request from end-users • Vote for acceptance at DAC face-2-face meeting • More donations expected in 2006 • Possible donation of VHDL/SystemC • Distribution agreement and license IP providers, EDA vendors, and general distribution to 3rd party

39. Conclusions • Accellera Technical activities successfully delivered critical standards over the past 12 months: • Fostered and Enabled Verilog 2005 and SystemVerilog 1800 • Development of VHDL 3.0 – expected to ballot and pass to IEEE in 2006 • OCI 1.0 – expected to pass ballot in Q3 2006 • OVL 2.0 • AMS LRM 2.4 and 3.0 as a preparation to integrate w/ SystemVerilog • PSL 1850 Assertions Language • ITC 2.0 including support for SystemC based on SystemVerilog DPI – expected in 2006