BPM card X generates VME interrupt

1. Ready signal from ADC clock mezzanine card on BPM card X BPM card X generates VME interrupt VME processor reads turn count from BPM card X Turn Count > 0, VME processor reads data from FIFO into EPICS Turn count = 0, VME processor invalidates current EPICS data EPICS posts a monitor event to all listening clients Oscillator output from ADC clock mezzanine (beam clock) READY signal from ADC clock mezzanine AWAK signal from ALICE Photo-Injector

2. Symptoms: Missing RDY signal -> No VME interrupt generated, no data read from FIFOs for that injection Glitching Beam Clock + Glitching RDY signal -> Digital card firmware logic receives incorrect signal levels, no VME interrupt, so no data read from FIFO for that injection Glitching Beam Clock + Good RDY signal-> VME interrupt generated on first clock glitch (RDY), VME processor attempts to read the FIFO whilst being written. Read + write disallowed, VME bus error generated, no data transferred from FIFOs.

3. Potential Temporary Solution? Generate 1 master interrupt from an “empty” BPM card generating the “NO_BEAM” interrupt 20.5us after AWAK arrives from ALICE. Use this interrupt to read all the cards after all beam has arrived from EMMA (with an additional sufficient delay over the 20.5us). No RDY signal and glitching RDY symptom is then negated. Is there valid data in the FIFOs when no RDY signal is observed? ADC beam clock would indicated that perhaps there is? Tested new interrupt scheme with pulse generator and observed good data. However, this also corresponds to a good RDY signal being ignored! Test on Monday/Tuesday with EMMA beam. Will require sacrificing 1 BPM card per crate (6) to perform the “NO_BEAM” master interrupt duty.