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Proposed AP2 line BPM readout card. 1. Variation on a theme – based on debuncher LLRF boards. Reuse uController, CPLD, Ethernet, SDRAM, Software. 2. Nim format, connects to ACNet via ethernet, local serial port for debug, download.
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Proposed AP2 line BPM readout card 1. Variation on a theme – based on debuncher LLRF boards. Reuse uController, CPLD, Ethernet, SDRAM, Software 2. Nim format, connects to ACNet via ethernet, local serial port for debug, download 3. Downconvert using AD8348 quadrature demodulator chip. Do low pass in analog. Digitize low pass output at 21MHz – ~35 samples per transfer 4. On board synthesizer to generate 53MHz from 10MHz reference using DDS in numerically controlled divider configuration, or lock to 53MHz reference 5. On board high speed DAC to generate test signals (e.g. self-test possible) 6. Large memory to hold long data records (readout optional); uController could be used for data reduction 7. LVDS port to exchange data, timing with other boards (optional) Ashmanskas, Hansen, Peterson 7/21/04
Debuncher Transfer Line BPM Card (2 BPMs/card) AD9201 x 4 EthRd 10 Bit A/D Lo Pass I/Q Dat EthWrt Ethernet WizNet IIM7010A AD8348 IN 0 A Eth Ad Lo Pass 10 Bit A/D 2RF/7 Eth Dat 10 Bit A/D Lo Pass I/Q Dat AD8348 A IN 0 B Lo Pass 10 Bit A/D D 2RF/7 USB Rd MSP430 uC Wrt 10 Bit A/D Lo Pass I/Q Dat AD8348 IN 1 A A Lo Pass 10 Bit A/D 2RF/7 SD RAM 16Mx16 EP1C6 Cyclone FPGA D 10 Bit A/D Lo Pass I/Q Dat AD8348 IN 1 B 53MHz I/O Lo Pass 10 Bit A/D 2RF/7 2RF Sync I/O SysClk 10/53MHz RJ-45 Ref Sdat I/O Ø Det 53MHz VXO AD9952 DDS Spare I/O Err Amp FB Ashmanskas, Hansen, Peterson 7/21/04
AD 8348 Ashmanskas, Hansen, Peterson 7/21/04
Post processing of Oscilloscope trace Oscilloscope trace with inline bandpass filter 5mV/Div Multiply by quadrature square wave to approximate mixer. Follow with 4 pole IIR to approximate analog low pass Multiply by Sine, Cosine follow with 100 nsec boxcar to show feasibility of oscilloscopes as BPMs Ashmanskas, Hansen, Peterson 7/21/04
Cost and Schedule Ball park cost $500 per NIM card. Four BPM plates per card Schematic is in progress. First pass next week Layout – 2 to 3 weeks after sign off on schematic Board fab 10 working days Assembly of first prototype 2-3 days. Initial debug of prototype 2 weeks. Software – first pass 2 weeks – talks to ethernet, reports raw data after being triggered; reporting sum, difference/sum to acnet is easy; more esoteric features TBD We need to start ordering parts soon (can we do so next week?) The plan is to having something ready to go in for testing by the end of the shutdown Ashmanskas, Hansen, Peterson 7/21/04