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Low-Power Design and Test Dynamic and Static Power in CMOS

Low-Power Design and Test Dynamic and Static Power in CMOS. Hyderabad, July 30-31, 2007 http://www.eng.auburn.edu/~vagrawal/hyd.html. Components of Power. Dynamic Signal transitions Logic activity Glitches Short-circuit Static Leakage. P total = P dyn + P stat

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Low-Power Design and Test Dynamic and Static Power in CMOS

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  1. Low-Power Design and TestDynamic and Static Power in CMOS Hyderabad, July 30-31, 2007 http://www.eng.auburn.edu/~vagrawal/hyd.html Low-Power Design and Test, Lecture 2

  2. Components of Power • Dynamic • Signal transitions • Logic activity • Glitches • Short-circuit • Static • Leakage Ptotal = Pdyn + Pstat Ptran +Psc+ Pstat Low-Power Design and Test, Lecture 2

  3. Power of a Transition: Ptran VDD Ron ic(t) vi (t) vo(t) CL R = large Ground Low-Power Design and Test, Lecture 2

  4. Charging of a Capacitor R t = 0 v(t) i(t) C V Charge on capacitor, q(t) = C v(t) Current, i(t) = dq(t)/dt = C dv(t)/dt Low-Power Design and Test, Lecture 2

  5. i(t) = C dv(t)/dt = [V – v(t)] /R dv(t) V – v(t) ─── = ───── dt RC dv(t) dt ∫───── = ∫ ──── V – v(t) RC -t ln [V – v(t)] = ── + A RC Initial condition, t = 0, v(t) = 0 → A = ln V -t v(t) = V [1 – exp(───)] RC Low-Power Design and Test, Lecture 2

  6. -t v(t) = V [1 – exp(── )] RC dv(t) V -t i(t) = C ─── = ── exp(── ) dt R RC Low-Power Design and Test, Lecture 2

  7. Total Energy Per Charging Transition from Power Supply ∞∞ V2 -t Etrans = ∫ V i(t) dt = ∫ ── exp(── ) dt 00 R RC = CV2 Low-Power Design and Test, Lecture 2

  8. Energy Dissipated per Transition in Resistance ∞ V2∞ -2t R ∫ i2(t) dt = R ── ∫ exp(── ) dt 0 R20 RC 1 = ─ CV2 2 Low-Power Design and Test, Lecture 2

  9. Energy Stored in Charged Capacitor ∞ ∞ -t V -t ∫ v(t) i(t) dt = ∫ V [1-exp(── )]─ exp(── ) dt 00 RC R RC 1 = ─ CV2 2 Low-Power Design and Test, Lecture 2

  10. Transition Power • Gate output rising transition • Energy dissipated in pMOS transistor = CV 2/2 • Energy stored in capacitor = CV 2/2 • Gate output falling transition • Energy dissipated in nMOS transistor = CV 2/2 • Energy dissipated per transition = CV 2/2 • Power dissipation: Ptrans = Etransα fck = α fck CV2/2 α = activity factor Low-Power Design and Test, Lecture 2

  11. Components of Power • Dynamic • Signal transitions • Logic activity • Glitches • Short-circuit • Static • Leakage Ptotal = Pdyn+ Pstat Ptran + Psc+ Pstat Low-Power Design and Test, Lecture 2

  12. Short Circuit Power of a Transition: Psc VDD isc(t) vi (t) vo(t) CL Ground Low-Power Design and Test, Lecture 2

  13. Short Circuit Current, isc(t) VDD VDD - VTp n-transistor cuts-off Vi (t) Vo(t) Volt VTn p-transistor starts conducting 0 Iscmaxf isc(t) Isc Time (ns) tB tE 1 0 Low-Power Design and Test, Lecture 2

  14. Peak Short Circuit Current • Increases with the size (or gain, β) of transistors • Decreases with load capacitance, CL • Largest when CL = 0 • Reference: M. A. Ortega and J. Figueras, “Short Circuit Power Modeling in Submicron CMOS,” PATMOS ’96, Aug. 1996, pp. 147-166. Low-Power Design and Test, Lecture 2

  15. Short-Circuit Energy per Transition • Escf =∫tBtE VDD isc(t)dt =(tE – tB) Iscmaxf VDD / 2 • Escf= tf(VDD - |VTp|- VTn) Iscmaxf / 2 • Escr= tr(VDD - |VTp| - VTn) Iscmaxr / 2 • Escf= Escr=0, when VDD= |VTp|+ VTn Low-Power Design and Test, Lecture 2

  16. Short-Circuit Energy • Increases with rise and fall times of input • Decreases for larger output load capacitance • Decreases and eventually becomes zero when VDD is scaled down but the threshold voltages are not scaled down Low-Power Design and Test, Lecture 2

  17. Short-Circuit Power Calculation • Assume equal rise and fall times • Model input-output capacitive coupling (Miller capacitance) • Use a spice model for transistors • T. Sakurai and A. Newton, “Alpha-power Law MOSFET model and Its Application to a CMOS Inverter,” IEEE J. Solid State Circuits, vol. 25, April 1990, pp. 584-594. Low-Power Design and Test, Lecture 2

  18. Short Circuit Power Psc = α fck Esc Low-Power Design and Test, Lecture 2

  19. Psc, Rise Time and Capacitance VDD VDD Ron ic(t)+isc(t) vi (t) vo(t) vo(t) CL tr tf R = large vo(t) ─── R↑ Ground Low-Power Design and Test, Lecture 2

  20. isc, Rise Time and Capacitance -t VDD[1- exp(─────)] vo(t) R↓(t) C Isc(t) = ──── = ────────────── R↑(t) R↑(t) Low-Power Design and Test, Lecture 2

  21. iscmax, Rise Time and Capacitance i Small C Large C vo(t) vo(t) iscmax 1 ──── R↑(t) t tf Low-Power Design and Test, Lecture 2

  22. Psc, Rise Times, Capacitance • For given input rise and fall times short circuit power decreases as output capacitance increases. • Short circuit power increases with increase of input rise and fall times. • Short circuit power is reduced if output rise and fall times are smaller than the input rise and fall times. Low-Power Design and Test, Lecture 2

  23. Summary: Short-Circuit Power • Short-circuit power is consumed by each transition (increases with input transition time). • Reduction requires that gate output transition should not be faster than the input transition (faster gates can consume more short-circuit power). • Increasing the output load capacitance reduces short-circuit power. • Scaling down of supply voltage with respect to threshold voltages reduces short-circuit power; completely eliminated when VDD ≤ |Vtp|+Vtn . Low-Power Design and Test, Lecture 2

  24. Components of Power • Dynamic • Signal transitions • Logic activity • Glitches • Short-circuit • Static • Leakage Low-Power Design and Test, Lecture 2

  25. Leakage Power VDD IG Ground Gate R Source Drain n+ n+ Isub IPT ID IGIDL Bulk Si (p) nMOS Transistor Low-Power Design and Test, Lecture 2

  26. Leakage Current Components • Subthreshold conduction, Isub • Reverse bias pn junction conduction, ID • Gate induced drain leakage, IGIDL due to tunneling at the gate-drain overlap • Drain source punchthrough, IPT due to short channel and high drain-source voltage • Gate tunneling, IGthrough thin oxide; may become significant with scaling Low-Power Design and Test, Lecture 2

  27. Subthreshold Current Isub = μ0 Cox(W/L) Vt2 exp{(VGS –VTH ) / nVt } μ0: carrier surface mobility Cox: gate oxide capacitance per unit area L: channel length W: gate width Vt = kT/q: thermal voltage n: a technology parameter Low-Power Design and Test, Lecture 2

  28. IDSfor Short Channel Device Isub= μ0 Cox(W/L)Vt2 exp{(VGS –VTH + ηVDS)/nVt} VDS = drain to source voltage η: a proportionality factor W. Nebel and J. Mermet (Editors), Low Power Design in Deep Submicron Electronics, Springer, 1997, Section 4.1 by J. Figueras, pp. 81-104 Low-Power Design and Test, Lecture 2

  29. Increased Subthreshold Leakage Scaled device Ic Log (Drain current) Isub 0 VTH’ VTH Gate voltage Low-Power Design and Test, Lecture 2

  30. Summary: Leakage Power • Leakage power as a fraction of the total power increases as clock frequency drops. Turning supply off in unused parts can save power. • For a gate it is a small fraction of the total power; it can be significant for very large circuits. • Scaling down features requires lowering the threshold voltage, which increases leakage power; roughly doubles with each shrinking. • Multiple-threshold devices are used to reduce leakage power. Low-Power Design and Test, Lecture 2

  31. Technology Scaling • Scaling down 0.7 micron by factors 2 and 4 leads to 0.35 and 0.17 micron technologies • Constant electric field assumed Low-Power Design and Test, Lecture 2

  32. Constant Electric Field Scaling • B. Davari, R. H. Dennard and G. G. Shahidi, “CMOS Scaling for High Performance and Low Power—The Next Ten Years,” Proc. IEEE, April 1995, pp. 595-606. • Other forms of scaling are referred to as constant-voltage and quasi-constant-voltage. Low-Power Design and Test, Lecture 2

  33. Bulk nMOSFET Polysilicon Gate Drain W Source n+ n+ L p-type body (bulk) SiO2 Thickness = tox Low-Power Design and Test, Lecture 2

  34. Technology Scaling • A scaling factor (S ) reduces device dimensions as 1/S. • Successive generations of technology have used a scaling S = √2, doubling the number of transistors per unit area. This produced 0.25μ, 0.18μ, 0.13μ, 90nm and 65nm technologies, continuing on to 45nm and 30nm. • A 5% gate shrink (S = 1.05) is commonly applied to boost speed as the process matures. N. H. E. Weste and D. Harris, CMOS VLSI Design, Third Edition, Boston: Pearson Addison-Wesley, 2005, Section 4.9.1. Low-Power Design and Test, Lecture 2

  35. Constant Electric Field Scaling Low-Power Design and Test, Lecture 2

  36. Constant Electric Field Scaling (Cont.) Low-Power Design and Test, Lecture 2

  37. Problem: A Design Example • A battery-operated 65nm digital CMOS device is found to consume equal amounts (P ) of dynamic power and leakage power while the short-circuit power is negligible. The energy consumed by a computing task, that takes T seconds, is 2PT. • Compare two power reduction strategies for extending the battery life: • Clock frequency is reduced to half, keeping all other parameters constant. • Supply voltage is reduced to half. This slows the gates down and forces the clock frequency to be lowered to half of its original (full voltage) value. Assume that leakage current is held unchanged by modifying the design of transistors. Low-Power Design and Test, Lecture 2

  38. Solution: Part A. Clock Frequency Reduction • Reducing the clock frequency will reduce dynamic power to P / 2, keep the static power the same as P, and double the execution time of the task. • Energy consumption for the task will be, Energy = (P / 2 + P ) 2T = 3PT which is greater than the original 2PT. Low-Power Design and Test, Lecture 2

  39. Solution: Part B. Supply Voltage Reduction • When the supply voltage and clock frequency are reduced to half their values, dynamic power is reduced to P / 8 and static power to P / 2. The time of task is doubled and the total energy consumption is, Energy = (P / 8 + P / 2) 2T = 5PT / 4 =1.25PT • The voltage reduction strategy reduces energy consumption while a simple frequency reduction consumes more energy. Low-Power Design and Test, Lecture 2

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