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Lecture 14: Completing the picture for basic control and datapath

Lecture 14: Completing the picture for basic control and datapath. Soon Tee Teoh CS 147. Control and Datapath (Figure 9-15, page 471). Extend. V C N Z. Branch Control. IR(8:6) || IR(2:0). PC. D Register File A B. RW DA AA. Address Instruction Memory Instruction.

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Lecture 14: Completing the picture for basic control and datapath

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  1. Lecture 14: Completing the picture for basic control and datapath Soon Tee Teoh CS 147

  2. Control and Datapath (Figure 9-15, page 471) Extend V C N Z Branch Control IR(8:6) || IR(2:0) PC D Register File A B RW DA AA Address Instruction Memory Instruction P J B L B C BA IR(2:0) Constant in Zero fill Instruction Decoder 1 0 MUX B MB MW D B A M F M R M P J B A A A B S D W W L B C FS V C N Z A B Function Unit F Data in Address Data Memory Data Out All the input controls colored RED 0 1 MUX D MD

  3. Need to determine input signals From Table 9-4, page 457: Operation MF Select G Select H Select FS F = A 0 0000 XX 0000 F = A+1 0 0001 XX 0001 F = A+B 0 0010 XX 0010 F = A+B+1 0 0011 XX 0011 F = A+B’ 0 0100 XX 0100 F = A+B’+1 0 0101 XX 0101 F = A-1 0 0110 XX 0110 F = A 0 0111 XX 0111 F = A ^ B 0 1X00 XX 1000 F = A v B 0 1X01 XX 1001 F = A xor B 0 1X10 XX 1010 F = A’ 0 1X11 XX 1011 F = B 1 XXXX 00 1100 F = sr B 1 XXXX 01 1101 F = sl B 1 XXXX 10 1110 See how FS gets converted to MF Select, G Select and H Select Exercise: Draw the circuit of this conversion

  4. Instruction Formats 15 9 8 6 5 3 2 0 Destination Register (DR) Opcode Source Register A (SA) Source Register B (SB) Register Format 15 9 8 6 5 3 2 0 Destination Register (DR) Opcode Source Register A (SA) Operand (OP) Immediate Format 15 9 8 6 5 3 2 0 Address (AD) Right Address (AD) Left Opcode Source Register A (SA) Jump and Branch Format From Figure 9-14, page 467

  5. Instructions and their Opcodes Instruction Opcode Mnemonic Format Description Move A 0000000 MOVA RD,RA R[DR] R[SA] Increment 0000001 INC RD,RA R[DR] R[SA] + 1 Add 0000010 ADD RD,RA,RB R[DR] R[SA] – R[SB] Subtract 0000011 SUB RD,RA,RB R[DR] R[SA] – R[SB] Decrement 0000110 DEC RD,RA R[DR] R[SA] – 1 AND 0001000 AND RD,RA,RB R[DR] R[SA] ^ R[SB] OR 0001001 OR RD,RA,RB R[DR] R[SA] v R[SB] XOR 0001010 XOR RD,RA,RB R[DR] R[SA] xor R[SB] NOT 0001011 NOT RD,RA R[DR] R[SA]’ Move B 0001100 MOVB RD,RB R[DR] R[SB] Shift Right 0001101 SHR RD,RB R[DR] sr R[SB] Shift Left 0001110 SHL RD,RB R[DR] sl R[SB] Load Immediate 1001100 LDI RD,OP R[DR] zf OP Add Immediate 1000010 STI RD,RA,OP R[DR] R[SA] + zf OP Load 0010000 LD RD,RA R[DR] M[SA] Store 0100000 ST RA,RB M[SA] R[SB] Branch on Zero 1100000 BRZ RA,AD if (R[SA]==0) PC PC + se AD Ranch on Negative 1100001 BRN RA,AD if (R[SA]<0) PC PC + se AD Jump 1110000 JMP RA PC R[SA] Note: “zf” means “zero fill” “se” means “sign extend” “sr” means “shift right” “sl” means “shift left” From Table 9-8, page 469

  6. Determining Control Word from Instruction • MW (Memory Write) for example is set to 1 if and only if Opcode begins with 01 • AA for example is simply SA • Full decoder: Instruction Destination Register (DR) Opcode Source Register A (SA) Source Register B (SB) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 3 3 IR9(IR14IR15) FS DA AA BA RW = IR14 MB = IR15 MD = IR13 MW = IR14.IR15 PL = IR14.IR15 JB = IR13 BC = IR9 Control Inputs

  7. Let’s examine some of these control inputs … • MB should be 1 whenever we want to select the immediate operand instead of Register A. We see that only LDI and ADI needs MB to be 1, and only LDI and ADI have a 1 in IR15. Therefore, just set MB to be IR15. • RW should be 1 whenever we want to write to register. The only instructions that don’t write to register are ST, BRZ, BRN and JMP. Notice that they all have a 1 in IR14. Therefore, just set RW to NOT(IR14).

  8. Let’s examine another control input: FS • Look at the last four bits of the Opcodes for the first 14 instructions (MOVA through ADI). Notice that they are exactly the bits for FS. • For example, the DEC opcode is 0000110 and the FS for F = A – 1 is 0110. • Therefore, we can connect IR(12:9) to FS. • However, we need to make an exception whenever we have a Branch or Jump instruction. When we have a Branch of Jump instruction, we want FS to be 0000, so that F = A. Now, BRN has a 1 in bit IR9, so we need to convert that to 0 for FS. • Hence, FS0 = IR9 . PL’ • (Remember, PL is 1 whenever we have a Branch or Jump instruction.)

  9. Branch Control • The Branch Control accepts as input PL, JB, BC, N and Z. PL: 1 if current instruction is a Jump or Branch instruction, 0 otherwise JB: 1 if current instruction is a Jump instruction, 0 otherwise BC: 1 if current instruction is “Branch if Zero”, 0 otherwise N: 1 if the output of the ALU is negative, 0 otherwise Z: 1 if the output of the ALU is zero, 0 otherwise • Output of Branch Control: S0S1 S1S0 = 00 if we want PC PC + 1 S1S0 = 01 if we want PC R[SA] (the Jump address) S1S0 = 10 if we want PC PC + se AD (the Branch taken address) PL JB BC N Z S1 S0 ______________________ 0 X X X X 0 0 1 1 X X X 0 1 1 0 1 X 0 0 0 1 0 1 X 1 1 0 1 0 0 0 X 0 0 1 0 0 1 X 1 0 Therefore, S0 = PL . JB S1 = PL . JB’ . BC . Z + PL . JB’ . BC’ . N

  10. Zero Fill • The Zero Fill component simulates converting an n-bit unsigned number to an m-bit unsigned number, where n < m. • For example, 1011 is the same as 00001011. • We simply copy the bits to the less significant bits, and insert zeroes in the more significant bits.

  11. Sign Extend • The Sign-Extend component simulates converting an n-bit number expressed in 2’s complement notation to an m-bit number expressed in 2’s complement notation. • For example 1011 becomes 11111011, and 0100 becomes 00000100. • We simply copy the bits to the less significant bits, and duplicate the original most significant bit to the more significant bits.

  12. Status bits of the Function Unit • The Function Unit outputs 4 status bits V, C, N and Z. V = 1 if overflow has occurred in the Arithmetic Unit. C = 1 if carry-out of the Arithmetic Unit is 1. N = 1 if the result of the Arithmetic Unit is negative. Z = 1 if the result of the Arithmetic Unit is zero. Let the inputs of the Function unit be A and B, and the output be F. Let A, B and F be n+1 bits long, so that the most significant bit is bit n, and the least significant bit is bit 0, then this is the circuit to obtain the status bits: ___________ Z = Fn + … + F0 N = Fn __ __ __ V = An . Bn . Fn + An . Bn . Fn C = carry_out of the Arithmetic Unit

  13. Add two instructions to the Instruction Set Architecture • Suppose you want to add the two instructions above to the ISA. • Note: All the opcodes are now 8 bits long, and instructions are now 17 bits long. • All original instructions have a 0 in IR16. • Assume that the content of the PC has the same number of bits as the content of the registers. • How would you change the control, datapath and instruction decoder to include these instructions? The opcode for SetPC is left open for you to decide. Instruction Opcode Mnemonic Format Description GetPC 11000010 GPC RD,OP RD  PC + zf OP SetPC ???????? SPC RA,OP PC  R[SA] + zf OP

  14. Add two instructions to the Instruction Set Architecture Answer: The new opcode for SetPC Instruction Opcode Mnemonic Format Description Move A 00000000 MOVA RD,RA R[DR] R[SA] Increment 00000001 INC RD,RA R[DR] R[SA] + 1 Add 00000010 ADD RD,RA,RB R[DR] R[SA] – R[SB] Subtract 00000011 SUB RD,RA,RB R[DR] R[SA] – R[SB] Decrement 00000110 DEC RD,RA R[DR] R[SA] – 1 AND 00001000 AND RD,RA,RB R[DR] R[SA] ^ R[SB] OR 00001001 OR RD,RA,RB R[DR] R[SA] v R[SB] XOR 00001010 XOR RD,RA,RB R[DR] R[SA] xor R[SB] NOT 00001011 NOT RD,RA R[DR] R[SA]’ Move B 00001100 MOVB RD,RB R[DR] R[SB] Shift Right 00001101 SHR RD,RB R[DR] sr R[SB] Shift Left 00001110 SHL RD,RB R[DR] sl R[SB] Load Immediate 01001100 LDI RD,OP R[DR] zf OP Add Immediate 01000010 STI RD,RA,OP R[DR] R[SA] + zf OP Load 00010000 LD RD,RA R[DR] M[SA] Store 00100000 ST RA,RB M[SA] R[SB] Branch on Zero 01100000 BRZ RA,AD if (R[SA]==0) PC PC + se AD Ranch on Negative 01100001 BRN RA,AD if (R[SA]<0) PC PC + se AD Jump 01110000 JMP RA PC R[SA] GetPC 11000010 GPC RD,OP R[DR] PC + zf OP SetPC 01110010 SPC RA,OP PC R[SA] + zf OP

  15. Add two instructions to the Instruction Set Architecture IR10 0 1 Register File A PC IR16 0 1 A Function Unit F Answer: How the datapath and control is changed to handle the two new instructions

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