About I2C BUS

1. About I2C BUS INHA UNIV RCSL kihong Choi

2. Contents • Features and Benefits of the I2C Bus • Applications and Configuration • The I2C BUS specification - Definition of I2C terminology - General characteristics - Transferring data specification - Arbitration & synchronization - Addressing mode • I2C Vs SPI

3. Features of the I2C Bus • Only two bus lines are required (SDA,SCL) • Simple master/slave relationships • Multi-master bus including collision detection and arbitration to prevent data corruption • Serial, 8-bit oriented, bidirectional data transfers 100kbit/s(standard mode), 400kbit/s(fast mode), 3.4Mbit/s(HS mode) • The number of ICs is limited only by a maximum bus capacitance of 400pF

4. Benefits of I2C Bus • Designer benefits - Functional blocks on the diagram correspond with the actual ICs - No need to design bus interface - ICs can be added to or removed from a system without affecting any other circuits on the bus - Fault diagnosis and debugging are simple - High noise immunity • Manufacturer benefits - The simple 2-wire minimizes interconnections - I2C-bus protocol eliminates the need for address decoders

5. Applications and Configuration • Applications - A system consists of at least one micro-controller and other peripheral devices( memory, I/O…) - Low-cost (simple bus, minimum hardware) - Minimum pin resources ( two signals) - Low speed data transfer ( serial bus) • Typical configuration

6. Definition of I2C terminology

7. General characteristics • Two bidirectional signals are defined - SDA : Serial Data , SCL : Serial Clock • Electrical interface - Devices drive signals using open-collector drivers - A pull-up resistor is used on each line - Signals are high unless driven low by at least one device(wired-AND)

8. Data validity • The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW.

9. START & STOP conditions • A HIGH to LOW transition on the SDA line while SCL is HIGH defines a START condition. • A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition. • START and STOP conditions are always generated by the master.

10. Data format • Every byte put on the SDA line must be 8-bits long. • Data is transferred with the most significant bit first. • Each byte has to be followed by an acknowledge bit.

11. Acknowledge (from receiver) • Follows each byte. • Low is acknowledge, High is negative acknowledge.

12. Synchronization ( at SCL ) • The wired-AND clock is used for synchronization - A bus master generates the clock - A bus slave can hold the clock low until it is ready

13. Arbitration ( at SDA ) • Arbitration takes place on the data bus(SDA) - As long as both send the same bit, there is no data corruption - The device sending the 1 loses arbitration

14. Format of 7-bit address mode • Addresses are seven bits long and uniquely identify a device • Address is sent by master as the first byte following a start condition • 8th bit of address selects operation - Read ( H ) : Master receives, slave transmits - Write ( L ) : Master transmits,slave receives • Addressed slave device responds with an acknowledgment

15. First byte

16. Format of 10-bit address mode • Two bytes are used : - First byte (7bit) : ”11110XX” - Second byte : “XXXXXXXX”

17. Modes of Operation - 1 • Master transmitter - Generates start and stop conditions - Generates clock signal - Writes data to bus • Master receiver - Generates start and stop conditions - Generates clock signal - Reads data from bus - Generates acknowledge bits

18. Modes of Operation - 2 • Slave transmitter - Writes data to bus - Can “ stretch” low clock periods • Slave receiver - Reads data from bus - Generates acknowledge bits - Can “Stretch” low clock period

19. I2C Vs SPI • SPI( Serial Peripheral Interface ) - made by MOTOROLA - CS, SCK, SI, SO Pin-out

20. Example I2C Based TV ( Phlips 55YP3C )