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A High dI/dt CMOS Differential Optical Transmitter for a Laser Diode

A High dI/dt CMOS Differential Optical Transmitter for a Laser Diode. HSSPG. Doctoral Dissertation Presentation by Sungyong Jung. Advisor: Martin A. Brooke. School of Electrical and Computer Engineering Georgia Institute of Technology, Atlanta, GA, 30332 March 28, 2002. Outline. HSSPG.

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A High dI/dt CMOS Differential Optical Transmitter for a Laser Diode

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  1. A High dI/dt CMOS Differential Optical Transmitter for a Laser Diode HSSPG Doctoral Dissertation Presentation by Sungyong Jung Advisor:Martin A. Brooke School of Electrical and Computer Engineering Georgia Institute of Technology, Atlanta, GA, 30332 March 28, 2002

  2. Outline HSSPG • Introduction • Background • Application • A Differential laser driver • Packaging Parasitic Consideration • Test Results • A Driver for LVDS Standard • Conclusion and Future Work

  3. HSSPG Introduction • Why Optical Interconnection? • Larger bandwidth than conventional interconnects • Low power consumption • Low parasitics • Smaller channel crosstalk • Shorter interconnection delays • Why CMOS? • Low power • High yield • Low cost • Higher degree of integration

  4. HSSPG Introduction • Objective • Development of drivers for optical interconnect • Using Available Standard Digital CMOS Technology • Predicting the behavior including parasitic models • Working at commercially interesting high speed with high output current

  5. HSSPG Background • Optical interconnection system

  6. Rates X1 X2 Y1 OC-1 and OC-3 0.15 0.35 0.20 OC-9 through OC-24 0.25 0.40 0.20 HSSPG Background • Eye Diagram • Visual method to measure the properties of a data stream • A composite of multiple puslses captured with a series of triggers based on the data-clock pulse • Jitter: close in the horizontal direction due to the variations in the pulse duration or the accuracy of the pulse stream’s clock • ISI, Noise: close in vertical direction

  7. HSSPG Background • Optical Sources • LED – Low speed communication • Simpler fabrication • Lower cost • High reliability • Less temperature dependence • Simpler driver circuitry • Higher linearity • LASER – High speed communication • High output power • Lower divergence degree The light output versus current characteristic of laser and LED.

  8. HSSPG Background • Optical Drivers An example of the laser driver An example of the LED driver circuit

  9. HSSPG Application • 2 & 3 Layer Thru-Silicon Optical Interconnect System • High bandwidth • Low loss • Small crosstalk • Short interconnect delay • Massively parallel interconnection

  10. InGaAsP InP/InGaAsP Emitter Detector Detector Amplifier Emitter Driver Silicon Circuitry Silicon Circuitry InGaAsP InP/InGaAsP Emitter Detector Emitter Driver Detector Amplifier Silicon Circuitry Silicon Circuitry HSSPG Application • Basic Structure of Thru-Silicon Interconnect

  11. 2 & 3 Layer Optical Link HSSPG • Integration of hybrid thin-film device • Separate fabrication • high yield • indep. Optimize • Reduce the packaging parasitics

  12. HSSPG Application • I-MSM photodetector • Larger area with lower capacitance than PiN detector • Metal fingers on the bottom • 0.7 A/W Responsivity • 250µm size: alignment tolerant • 1.1 GHz operation in this size • Resonant Cavity LED • Improved spectral purity • 100µm square device • Long wavelength (.3m) • 100 Mbps operation in this size

  13. HSSPG Application • Receiver • Single-ended • 0.8 um Si CMOS technology

  14. 1.5 V 13.5 mV 500 5 mV/ mV/ div div -3.5 V -6.5 mV 19.04 ns 50 ns /div -244 ns 2 ns /div 256 ns -960 ps HSSPG Application • Test Results of Integrated Receiver at 155 Mbps Eye diagram for 50um MSM Pulse diagram for 50um MSM

  15. HSSPG Application • LED Driver • Single-ended • 0.8 um CMOS technology

  16. HSSPG Application • Test Results of Integrated Transmitter at 155 Mbps 250um & 100 um InGaAlAs integrated TX

  17. HSSPG Application • Test setup • 144 pin PGA package Test board with a bonded chip Test setup block diagram

  18. HSSPG Application • Test result of 2-layer interconnection • PRBS 27-1 at 40 Mbps, 1x10-9 BER 2-layer diagram 40 Mbps RX output

  19. HSSPG Application • 3-layer link 3-layer stacked chip The measured eye diagram of three-layer system at 1 Mbps

  20. A Differential Laser Driver Specification Predetermined Goal of Design Speed Greater than 1Gbps Output Current DC range: 0 – 30 mA AC range: 0 – 180 mA Current Density Less than 30uA/1um square meter HSSPG • Design Preview • High speed with high output current • Differential topology • Packaging parasitics • NSC 0.35 um Technology • 5.9E10-11 BER at 1 Gbps

  21. HSSPG A Differential Laser Driver • Model of a Laser • Lb: Induction due to wire bond • Cp: Capacitance of the laser chip • Rs: Metal contacts • Rj: Resistance from p-n junction • Cj: Capacitance from p-n junction

  22. HSSPG A Differential Laser Driver • Circuit Schematic • 180 mA peak-to-peak modulation current • 30 mA laser biasing current • 0.35 um Si CMOS technology Simulation result at 1 Gbps

  23. HSSPG A Differential Laser Driver • Simulation Results Transient response at 2 Gbps • Top: Input pulse • Middle: Pulse output • Bottom: eye diagram Temperature simulation at 27 and 200 • Top: Pulse output at 27 • Second: Eye diagram at 27 • Third: Pulse output at 200 • Bottom: eye diagram at 200

  24. HSSPG A Differential Laser Driver • Scalability • 0.18 um technology Transient response at 10 Gbps • Top: Input pulse • Middle: Pulse output • Bottom: eye diagram MAGIC layout • Scale factor: 1.944 • Bandwidth: gm/C

  25. Packaging Parasitics HSSPG • Background – delta-I noise • Degrade the edge rate • Reduce noise margins • Cause false switching

  26. HSSPG Packaging Parasitics • Printed Circuit Board Design PCB for TX testing Metal line in PCB

  27. HSSPG Packaging Parasitics • Modeling of the parasitics • ADS spice model generator • PCB trace

  28. HSSPG Packaging Parasitics • Modeling of the parasitics • Inductance of Bonding wires o: the permeability of free space, r: the relative permeability of the bonding wire material, d: the diameter of the boding wire, l: is the length of the bonding wire, : the skin effect factor ds is: the skin depth of the bonding wire material • : the resistivity of the bonding wire material f: the frequency

  29. Parameter Value Parameter Value L1 105 nH C4 0.367874 pF L2 1.38664 nH C5 0.367874 pF L3 1.38664 nH C6 0.367874 pF L4 1.38664 nH R1 0.1  L5 1.38664 nH R2 0.0280365  L6 1.38664 nH R3 0.0280365  L7 3.996 nH R4 0.0280635  C2 0.367874 pF R5 0.0280635  C3 0.367874 pF R6 0.0280635  HSSPG Packaging Parasitics • The value of parasitics

  30. HSSPG Packaging Parasitics • Solutions for reducing delta-I noise • Differential topology • Eliminate noise by using symmetric but inverse current flowing path to the power supply lines. • Decoupling Capacitor • Maintain the constant dc power supply levels.

  31. HSSPG Packaging Parasitics • Bias Stablization Simulation Single-Ended Version Bias Current (Has a Signal Component) Differential Version Bias Current (No Signal Component)

  32. HSSPG Packaging Parasitics • The model of decoupling capacitors • ESR: Equivalent series resistance • ESL: Equivalent series inductance

  33. HSSPG Packaging Parasitics • Parasitic effect simulation 1 nF Decoupling capacitance 10 nF Decoupling capacitance Simulation result with parasitic model • No open eyes Simulation result with ideal decoupling capacitor

  34. HSSPG Packaging Parasitics • Simulation with real model • ESR: 0.855 Ohm • ESL: 1.12 nH • C: 10.015 nF Simulation result with real decoupling capacitor model

  35. HSSPG Decoupling capacitor The driver circuit Decoupling capacitor The driver Packaging Parasitics • Chip layout and farbrication • Layout in Cadence • Minimized depletion capacitance • NSC 0.35 um technology

  36. Test Results HSSPG • Test setup • Chip-on-Board (COB) technology Test board with a bonded chip Test setup block diagram

  37. HSSPG Test Results • Transient response test • 0.1 uF decoupling capacitor • 27-1 NRZ PRBS • 200 Mbps operation

  38. HSSPG Test Results • Transient response test @ 622 Mbps • 10 nF decoupling capacitor • 27-1 NRZ PRBS • 10-11 BER

  39. HSSPG Test Results • Transient response test @ 900 Mbps • 10 nF decoupling capacitor • 27-1 NRZ PRBS • 0.210-11 BER

  40. HSSPG Test Results • Transient response test @ 1 Gbps • 10 nF decoupling capacitor • 27-1 NRZ PRBS • 5.910-11 BER

  41. HSSPG Test Results • Analysis with additional parasitics Simulation results at 1 Gbps • Top: Input pulse • Middle: Pulse output • Bottom: eye diagram

  42. A Driver for LVDS Standard Specification Predetermined Goal of Design Speed Up to 1Gbps Input magnitude > 400 mV Power supply 2.5 V Output current DC range: 0 – 30 mA AC range: 0 – 40 mA Current density Less than 30uA/1um square meter HSSPG • Objectives • Design a laser driver compatible with LVDS IEEE standard

  43. HSSPG A Driver for LVDS Standard • Pre-driver circuit design

  44. HSSPG A Driver for LVDS Standard • Overall circuit schematic Circuit diagram Simulation result at 1 Gbps

  45. Receiver DAC Decoupling Capacitor Transmitter HSSPG A Driver for LVDS Standard • Chip layout and fabrication • Layout in MAGIC • TSMC 0.25 um technology

  46. Conclusion and Future Work Ref. Process Channel Length [m] Speed [Gbit/s] Max. Output Current [mA] Eye Diagram BER Remark This Work CMOS 0.35 1 180 Yes Yes -Measure in packaging -Electrical test This Work CMOS 0.25 1 40 No No -Only simulation results [27] CMOS 0.5 m 2.5 1.6 Yes Yes -On-wafer measure -Optical test [28] CMOS 1.2 m 1 1.2 Yes Yes -Optical test [29] CMOS 1.0 m 0.622 25 Yes No -On-wafer measure -Optical test [21] CMOS 0.8 m 1.5 GHz NA No No -On-wafer measure -Electrical test HSSPG [33] CMOS 0.35 m 1 NA No No -Only simulation results • Comparison • Highest current driving capability at Gbps speed • Not many drivers with BER and/or eye-diagram

  47. HSSPG Conclusion and Future Work • Conclusion • High-speed and high-current optical transmitter were designed, simulated, fabricated, and tested using CMOS technology • Packaging parasitics was modeled and incorporated in the driver design • Differential topology was employed • the model of decoupling capacitor was included in the simulation and proper value was estimated and verified • The driver compatible with LVDS IEEE standard was designed, simulated, and fabricated

  48. HSSPG Conclusion and Future Work • Future Work • Compatible receiver part for transceiver system • Additional function blocks such as a multiplexer or a predistorter circuit • Verification of LVDS driver circuitry

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