High Speed ADC

1. High Speed ADC Prepared by: Mina AdelOmar Hassan El Sayad GehadHesham Omar Mohsen Supervised by:Dr. Mohamed Abd El Ghany

2. Outline • High Speed Digital Design • Analog to Digital Converter • A Dual Mode 7-Bit A/D Converter in 0.25 micron digital CMOS • 6 Bit 2.5GS/s Flash ADC using Comparator Redundancy for Low Power in 90 nm CMOS

3. High Speed Digital Design

4. Background • High speed digital design in contrast to digital design which has lower speed. Emphasize the behavior of passive circuit elements • These passive circuits’ elements may include wires, circuit board and integrated circuit package that make up a digital product. • At low speed passive circuits elements are just part of product packaging • At high speed they directly affect electrical performance

5. Architecture and layout • Architecture : Knowing the parts (components ) that make up your complete system . • Layout : like how the copper wires on the PCB are cut into traces of strip line and micro strip. All the devices are also placed on the board either on the top or bottom layer and interconnections are made through an intensely woven inner layer of signals. Usually we use programs to draw it like L-edit and MICROWIND.

6. Factors to be considered before building the board • Ground bounce(associated with transistor switching where the gate voltage can appear to be less than the local ground potential, causing the unstable operation of a logic gate ) • Cross talk (interaction between signals) • Power supply noise • EMI factors • Radiation • Electrostatic discharge

7. Signals in high speed design are electrical in nature and consist of current flowing through the wires. The following principles of mutual inductance, mutual capacitance will affect the response, quality of the electrical signal when it flows through a copper trace wire.

8. Mutual Capacitance Two conductors in close proximity to each other, carrying a signal, share an electric field and this electric field causes an unintentional current flow between them. The coupling between them acts like a shunt capacitor. A capacitor blocks DC but passes high frequency signals. Given the value of C and frequency f, then for a sinusoidal input the equation that governs the effective impedance is given by : Xc = 1 / 2 * pi * f * C The equation shows that the effective capacitive of the circuit starts to decrease as the frequency of the circuit gets higher. This means that capacitors start becoming more like short circuits at higher frequencies .

9. Mutual Inductance The current forms loops in circuit. These loops are sometimes simple or can be complex. Every loop of current has inductance L associated with it. A series inductor passes DC but blocks high frequency noise. Given a value of L and also given the frequency f, then for a sinusoidal input the equation that governs that effective impedance magnitude is given by: Xl = 2 * (pi) * f(frequency) * L From the equation we see that with the increasing frequency of systems the effective impedance of the given circuit increases. This means that inductor start becoming more like open circuits at higher frequencies.

10. These properties can help us find the effective capacitance or inductance present in a circuit due to mutual inductance and capacitance. These are the parasitic elements involved in a circuit and they have the ability to destroy a good frequency response.

11. Current Loops It has already been stated that current flows in loops, these loops form the return path. The problem with high speed digital design is that current bunches together and forms very tight loops that try to follow the path as close as possible

12. Characteristic impedance • Characteristic impedance is one of the properties of transmission lines. • Characteristic impedance is the ratio of voltage to current in a transmission line. • In theory a perfectly matched transmission line will be devoid of any reflections from the far end and thereby will not have any reflected signal causing an addition or subtraction to the original signal at the near end and so on. • Reflections on a transmission line can be avoided by using terminations to the transmission line. • The most popular terminations used in the digital logic are either end termination or series termination.

13. End Termination • End terminations use a resistor or split a pair of resistors which connect to VCC and ground respectively with the line as the reference point. The Figure show : Split Resistor Termination

14. Series Termination • Most common method of terminations is the one used in point to point signals. This is the series termination. A resistor of matched value to the impedance of the line is put in series to the source before the transmission line. The resistor accomplishes the cancellation of reflections The Figure show : Series Termination

15. Analog to Digital Converter

16. Introduction • ADC = Analog-Digital-Converter • Conversion of audio signals (mobile micro, digital music records, ...) • Conversion of video signals (cameras, frame grabber, ...)

17. Definition • Most signalswewant to process are analog • i.e.: they are continuous and cantake an infinitenumberof values x(t) t

18. Definition • Digital systemsrequirediscrete digital data • ADC converts an analog information into a digital information ? Digital System Digital Analog

19. ADC - Scheme • Analog input can be voltage or current (in the following only voltage) • Analog input can be positive or negative (in the following only positive)

20. ADC Values • Resolution N: number of discrete values to represent the analog values (in Bit) • 8 Bit = 28 = 256 quantization level, • 10 Bit = 210 = 1024 quantization level • Reference voltageVref: Analog input signal Vin is related to digital output signal Dout through Vref with: Vin = Vref·(D02-1 + D12-2 + … + DN-12-N) • Example: N = 3 Bit, Vref = 1V, Dout = ‘011’ => Vin = 1V · ( 2-2 + 2-3) = 1V · (0.25 + 0.125) = 0.375V Vin Dout = D0D1…DN-1 ADC Vref

21. ADC Values • VLSB : Minimum measurable voltage difference in ideal case (LSB – least significant Bit) • VLSB = Vref / 2N • Vin = VLSB(D02N-1 + D12N-2 + … + DN-120) • Example: N = 3 Bit, Vref = 1V, Dout = ‘011’ => VLSB= 1V / 23 = 0.125V => Vin = 0.125V · ( 21+ 20) = 0.125V · 3 = 0.375V • ΔV: Voltage difference between two logic level • Ideal: all ΔV = VLSB • VFSR: Difference between highest and lowest measurable voltages (FSR – full scale range)

22. Ideal ADC

23. Types of ADCs • Low-to-medium speed and high accuracyADCs • Integrating • Medium speed and medium accuracyADCs • Successive Approximation • Algorithmic • High speed and low-to-medium accuracy ADCs • Flash • Two-Level Flash • Pipelined

24. Flash ADC • Vin connected with 2N -1comparators in parallel • Comparators connected to resistor string • Thermometer code • R/2-resistors on bottom and top for 0.5 LSB offset

25. VIN + - VOUT VREF Flash ADC Comparator is one use of an Op-Amp

27. Flash ADC: pros and cons Very fast  High effort for the 2N-1 comparators  High Area / High Power  Recommended for 6-8 Bit and less

29. A Dual Mode 7-Bit A/D Converter in 0.25 micron digital CMOS

30. Introduction • Used in hard disk drive read channels • It has 2 modes • 6-bit resolution at full speed • 7-bit more accurate mode operating at lower speed • CMOS Technology : 0.25 um • Speed : • up to 700MSamples/s in the 6-bit • up to 200MSamples/s in the 7-bit • Area : 0.45 sq. mm • Power consumption : less than 187m W

31. The input is sampled and held by the sample and hold (S/H) circuit.

32. The output of the S/H is processed by the 7-bit interface • It selects between the 2 modes: • 6-bit mode, it behaves like a short circuit. • 7-bit mode, a circuit logic method is used to obtain a 7 bit output

33. The output from the 7 bit interface is fed into the comparator array • It converts the input signal into a digital thermometer code.

34. This digital output is connected to a bubble correction logic • It converts the thermometer code into a 1 of 64 code.

35. This in turn is fed into a ROM type encoder that generates the final 6-bit digital output.

36. Sample and Hold Circuit • A sample and hold circuit is an analog device that samples (captures, grabs) the voltage of a continuously varying analog signal and holds (locks, freezes) its value at a constant level for a specified minimum period of time.

37. Sample and Hold Circuit • It employs a pseudo-differential architecture made of two single ended S/H circuits • An important feature, it uses two inter-leaved S /H circuits operating at half the sampling frequency: • The input signal is first buffered by an input buffer before being fed into the two interleaved paths. • The two inter-leaved outputs are recombined using a set of pass gates. • The re-combined signal is fed into a common output buffer that drives the comparator array.

38. Sample and Hold Circuit The inter leaving has two advantages : • the acquisition time for each S /H is twice that available if a single S /H circuit was used  faster speed  higher frequency • The final output of the S/H is a 'held' signal for an entire clock interval. This eases the design of the output buffer that drives the comparator array. The disadvantage with inter-leaving is the mismatch between the two channels

39. Comparator • The output of the S/H circuit is compared against 2^N references (Vref) . • The differences are then amplified by the preamps

40. First Stage Preamp • During an auto zero periods: the reference voltages are connected to one side of the input capacitors • For conversion cycles: the capacitors are connected to the S /H output instead of the generator. • The voltage stored on the capacitors = reference voltage – input voltage. • This is how each comparator detect if the input voltage is higher or lower than the reference voltage thus the output is 1 or 0.

41. Comparator • The outputs from the preamps are latched by the latches. • The latches take the analog input (now amplified by the preamps) and convert them to ones or zeros. • Its output is in the form of a thermometer output

42. Explanation : Thermometer output • The input voltage is compared with all reference voltages from down to up • If input voltage > Vref output = 1 • If input voltage < Vref output = 0 • A series of ones is obtained until the reference voltage value is higher than the input voltage which result zero outputs. • The encoder’s binary output is equal to the order of the last reference step with output 1 , also equal to total numbers of ones – 1 • It looks like a thermometer tube: Its liquid level increases gradually from down to up until it reaches a stable value

43. 0 1.6 Input: 00011111 0 1.4 0 1.2 1 1 Output: 100 1V 1 0.8 1 0.6 1 0.2 to 0.4 1 0 to 0.2

44. Comparator • The bubble correction logic eliminates some types of bubbles and converts the thermometer code into a '1 of 64' code.

45. Explanation : Bubble error (sparkles) • An error can occur in the thermometer output when we receive a zero in the middle of the ones series due to a wrong output from the comparator • This is called the bubble error (sparkle). It is like an air bubble gap in the middle of our thermometer liquid. • This can be fixed by an error correction circuit that have multiple methods to detect any incorrect outputs in the middle of the thermometer output and fix it

46. 0 1.6 Input: 00011011 0 1.4 0 1.2 1 1 Output: ERROR 1V 1 0.8 0 0.6 1 0.2 to 0.4 1 0 to 0.2

47. Comparator • The encoder then encodes this to a 6 bit output.

49. Operation of the 7-bit mode (Dual Mode) • 7-bit operation is achieved here using a two step technique • First step: a 6-bit A/D conversion performed with an analog voltage = input voltage + ½ LSB. • The LSB from this operation is stored in a 1-bit memory element D. • Second step: a normal 6-bit A/D conversion performed without adding the ½ LSB to the input. • The 7th bit is obtained by Xor-ing the new LSB with the previous saved one

50. Operation of the 7-bit mode (Dual Mode) • If the input were to lie in the upper half of a 6-bit LSB interval, adding the 1/2 LSB would push the result of the conversion into the next higher step. Thus, the results from the first and second steps would be different. • An important advantage : digital bits from the first step are not required for the second step. Which is in contrast to conventional two step architectures that limits the speed of operation. • During both steps, the output of the S /H itself does not change from the first step to the second.