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PhTiMes

PhTiMes. Standard VME crate PhTDC – Data driven TDC, VME A24D32 module based on the HPTDC chip. 32/64 dECL channels (25/100 ps resolution). Total 16 board. MVME – standard VME CPU PhLoM – Phobos Logic Module Busy-free. 100 Mbps. MVME. PhLoM. PhTDC. CC mCC L0 L1/ evN.

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PhTiMes

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  1. PhTiMes • Standard VME crate • PhTDC – Data driven TDC, VME A24D32 module based on the HPTDC chip. 32/64 dECL channels (25/100 ps resolution). Total 16 board. • MVME – standard VME CPU • PhLoM – Phobos Logic Module • Busy-free 100 Mbps MVME PhLoM PhTDC CC mCC L0 L1/ evN We expect rather low data rate, 6 MB/s max, this correspond to 15K hits/sec. Therefore Slink is not necessary. This greatly simplifies the integration to the existing DAQ. The data will be sent to event builder over Fast Ethernet exactly like it is done in the existing VME crate. a Problem. Current version of the HPTDC have a problem with L1 buffer especially when chip runs at Vcc>2.4 V Workaround. It is proven in KABES that it is possible to run at Vcc=2.4 V. In a worst case scenario we will have resolution 98 ps (48 ps RMS)

  2. Triggering Search window 40 MHz RF, 36 ns L1 settling time PhL1 Hits • Triggering of the PhTiMeS • No Phobos L0. • Phobos L1 (PhL1) is synchronized with the RF and have constant delay relative to the triggering bunch crossing. • RF is not measured in the TDC. • Upon receiving of the PhL1 the PhTiMeS calculates a region of interest (ROI) by subtracting the constant ‘L1 Settling Time’ from the current clock position. Obviously, the width of the ROI should cover spread of the hits plus one clock. All hits from the ROI will be transferred to an L1 output buffer (circular buffer, 256 word deep). • Note. The maximum bunch filling of the RHIC is 112, in this case the distance between the possible bunch crossing is 3 RF ticks = 108 ns.

  3. Triggering Search window 40 MHz RF, 36 ns Hits L1 settling time PhL1 Trigger latency HPTDC Trigger • Triggering of the PhTiMeS • No Phobos L0. • Phobos L1 (PhL1) is synchronized with the RF and have constant delay relative to the triggering bunch crossing. • RF is not measured in the TDC. • Upon receiving of the PhL1 the PhTiMeS calculates a region of interest (ROI) by subtracting the constant ‘L1 Settling Time’ from the current clock position. Obviously, the width of the ROI should cover spread of the hits plus one clock. All hits from the ROI will be transferred to an L1 output buffer (circular buffer, 256 word deep). • Note. The maximum bunch filling of the RHIC is 112, in this case the distance between the possible bunch crossing is 3 RF ticks = 108 ns.

  4. PhTDC32-25 HPTDC TTC bus (10 pins) JTAG bus (10pins x 2) VMEP1 XC18V04 HPTDC Input channells connector 1 (34pins x 2) XILINX FPGA XC2V1000-4BG575 (1500,2000) SN74ABTE18245 (246)DGGR HPTDC VMEP2 Input channells connector 2 (34pins x 2) HPTDC SN74CBTD16211DGGR HPTDC SN65LVDT34D

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