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Basic Design Approach of FSM. Six Step Process. 1. Understand the statement of the Specification 2. Obtain an abstract specification of the FSM 3. Perform a state minimization 4. Perform state assignment 5. Develop Verilog description of the FSM
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Basic Design Approach of FSM Six Step Process 1. Understand the statement of the Specification 2. Obtain an abstract specification of the FSM 3. Perform a state minimization 4. Perform state assignment 5. Develop Verilog description of the FSM 6. Use logic synthesis tools to generate gate-level circuits 3, 4, can be done by logic synthesis tools
Example: Vending Machine FSM General Machine Concept: deliver a can of coke-cola after 15 dollars deposited single coin slot for $5, $10 no change Step 1. Understand the problem: Draw a picture! Block Diagram 5 Coin Coke-cola Vending Open 10 Sensor Machine Release FSM Mechanism Reset Clk
Vending Machine Example Step 2. Map into more suitable abstract representation Tabulate typical input sequences: three $5 $5, $10 $10, $5 two $10 two $5, %10 Reset S0 F T Draw state diagram: S1 S2 Inputs: F, T, reset Output: open T F T F S4 S6 S3 S5 [open] [open] [open] F T S7 S8 [open] [open]
Present Next Output State T F State Open $0 0 0 $0 0 0 1 $5 0 1 0 $10 0 1 1 X X T $5 0 0 $5 0 0 1 $10 0 1 0 15 0 1 1 X X F $10 0 0 $10 0 0 1 15¢ 0 1 0 15¢ 0 1 1 X X $15 X X $0 1 Vending Machine Example Step 3: State Minimization Inputs Reset $0 F $5 F $10 F, T $15 [open] reuse states whenever possible Symbolic State Table
Verilog Development • Mealy machine or Moore machine? • If the outputs are functions of the internal state? • Separate combinational circuits and FF’s • combinational circuits • Boolean functions of next state • Boolean functions of the outputs • FF’s • current state <= next state