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Chapter 4

Chapter 4. Combinational Logic Design Principles. Combinational Logic Circuit. Combinational Logic Circuit. Preface. Combinational Logic Circuit. Sequential Logic Circuit. Input. Output. Combinational Logic Circuit. Feedback Logic. Logic Gates. Sequential Logic Circuit. Input.

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Chapter 4

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  1. Chapter 4 Combinational Logic Design Principles

  2. Combinational Logic Circuit Combinational Logic Circuit Preface Combinational Logic Circuit Sequential Logic Circuit Input Output Combinational Logic Circuit Feedback Logic Logic Gates Sequential Logic Circuit Input Output

  3. Logic Abstract Get Truth Table or Logic Function Using Logic IC Module Simplify Logic Function Draw Logic Circuit Using PLD or CPLD Program by VHDL or ABEL Design Step Emphasis

  4. 4.1 Switching Algebra Boolean Algebra (1854) 1.Axioms George Boole 1815-1864 Positive-Logic 1-High 0-Low Negative-Logic 0-High 1-Low Default as Positive-Logic

  5. (A1) (A2) (A3) (A4) (A5)

  6. 2.Theorems (T1) Identities Single-Variable Theorems (T2) Null elements (T3) Idempotency (T4) Involution (T5) Complements

  7. (T6) Commutativity (T7) Associativity (T8) Distributivity (T9) Combining

  8. (T10) Covering (T11) Consensus (T12) DeMorgan’s

  9. Prove by using Truth Table X Y 0 0 1 1 1 1 0 1 0 1 1 0 1 0 0 1 1 0 1 1 0 0 0 0 Augustus De Morgan 1806-1871 (T13) Extending 1

  10. 3.Rules I. Replacing Ex.4-1 If then n-Variable DeMorgan’s theorems

  11. II. Shannon’s Expansion 1937 Claude Elwood Shannon 1916-2001 Prove?

  12. III. Inversion whole Be known Ask for Principle of Inversion: Retain of original Sequence of Operation First “·” and Secend “+” ■Swapping “+” and “·”. ■Swapping “1” and “0”. ■Complementing all Uncomplemented variables, and Uncomplementing all Complemented ones. Ex.4-2 · ( ) · ( ) Or

  13. IV. Duality Positive Logic Negative Logic Retain of original Sequence of Operation Principle of Duality: ■Swapping “+” and “·”. ■Swapping “1” and “0”. Distributivity Ex.4-3

  14. 4.Standard Representations of Logic Functions AND-OR Sum of products Base Rpresentations OR-AND Product of sums NAND-NAND NOR-NOR AND-OR-NOT

  15. 5.Minterm and Maxterm ■An n-variable minterm is a normal product term with n literals. 2n such product terms. mi i=0,1, …,2n-1 ■An n-variable maxterm is a normal sum term with n literals. 2n such sum terms. Mi i=0,1, …,2n-1

  16. 3-variables A,B,C Ex.4-4 23(8) minterms m0 m1 m2 m3 m4 m5 m6 m7 A B C 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 1 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 1 0 1 0 0 0 0 0 1 0 0 1 1 1 0 0 0 0 0 0 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 1 Every minterm is exclusive. if

  17. 3-variables A,B,C Ex.4-5 23(8) maxterms M7 M6 M5 M4 M3 M2 M1 M0 A B C 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 0 1 0 0 1 0 1 1 1 1 1 0 1 1 0 0 1 1 1 1 1 1 0 1 1 1 0 1 1 0 1 0 0 1 1 1 1 1 0 1 0 1 1 1 0 1 1 1 1 1 0 1 1 0 1 0 1 1 1 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 0 Relationship between minterms and maxterms: Every maxterm is exclusive. if

  18. Ex.4-6 F’ A B C F 0 0 0 1 m0 0 M0 0 0 1 m1 0 1 m2 1 0 1 0 0 M2 “0” 0 1 1 m3 1 0 Minterm “1” m4 1 0 0 0 1 M4 m5 0 1 0 1 1 M5 0 1 1 0 1 m6 0 1 1 1 m7 1 “0” Maxterm “1”

  19. 4.2 Combinational Circuit Analysis ■Behave of the circuit. 3 Invertors 4 AND Gates ■Get different circuit structure. 3 OR Gates A A B B C C B A F C C B

  20. A B F C A B F C A B F C A B F C 1 Invertor 2 AND Gates AND-OR 1 OR Gate 1 Invertor OR-AND 1 AND Gate 2 OR Gates 1 Invertor Faster NAND-NAND 3 NAND Gates 1 Invertor Faster NOR-NOR 3 NOR Gates

  21. A B F C NAND-NAND AND-OR De Morgan Theorems: HOMEWORK: P231 4.9 4.14(Using Theorems)

  22. Logic Abstract Get Truth Table or Logic Function Using Logic IC Module Simplify Logic Function Draw Logic Circuit Using PLD or CPLD Program by VHDL or ABEL 4.3 Combination-Circuit Synthesis Design Step √ √

  23. A B F C Ex.4-7 Design a circuit for vote. One manager, and two clerks. If the manager dissents, then the proposal isn’t passed . If the manager agrees, and any other clerk agrees too, then the proposal is passed. Assume: manager is A, clerks are B and C. agreeing-1,and disagreeing-0 A B C F Ouput is F. 0 0 0 0 0 0 1 0 passing-1,and not passing-0 0 1 0 0 0 1 1 0 1 0 0 0 1 1 0 1 1 1 0 1 1 1 1 1 NAND-NAND AND-OR

  24. A B F C A B C F Combinational-Circuit Minimization ■Minimizing the number of first-level gate. ■Minimizing the number of inputs on each first-level gate. ■Minimizing the number of inputs on the second-level gate. First-level gate Inputs on first-level gate

  25. 1.Minimization using Boolean Theorems Combining Covering Consensus Extending 1

  26. 2.Karnaugh Maps 1951 Edward W Veitch Truth Figure 0 1 1953 m0 m1 2-variables 0 1 m2 m3 Maurice Karnaugh 00 01 11 10 3-variables For using Combining! 0 m0 m1 m3 m2 1 m4 m5 m7 m6 Gray Codes 11 10 00 01 m0 m1 m2 m3 00 4-variables m4 m5 m7 01 m6 m12 m13 11 m15 m14 10 m8 m9 m11 m10

  27. Using Method of Karnaugh Maps Covering Logic Adjacent 1-cells Only one variable is different. For Using Combination Theorem. Logic Adjacent 1-cells: ■Immediately adjacent ■Wraparound ■Symmetrical Remove i-variables from product term. Covering Principles: ■Each circle covers has 2i1-cells. ■Range of each circle covers is the largest possible. ■Quantity of circle covers is the least possible. ■Each circle covers has one 1-cell different from others at least.

  28. Ex.4-8 Simplifying Truth Table Distinguished 1-cell “0” A B C D F 0 0 0 0 1 “1” 00 01 11 10 0 0 0 1 1 00 0 0 1 0 0 1 1 0 0 01 0 0 1 1 0 1 0 1 1 0 1 0 0 1 11 1 1 1 1 0 1 0 1 0 1 10 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 0 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 Sum of products 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1

  29. Product of sums Distinguished 0-cell 00 01 11 10 00 1 1 0 0 01 1 0 1 1 “0” 11 1 1 1 1 “1” 1 10 0 1 1

  30. “Don’t care” Input Combinations Optional term BCD(8421) 1010~1111 Inhibiting term Turn clockwise, if A=1 Turn anticlockwise, if B=1 Stop ,if C=1 A,B and C are inhibiting variables Ex.4-9 Inhibiting terms:

  31. Not using Inhibiting terms 00 01 11 10 00 1 0 1 1 01 1 0 0 1 11 0 0 0 0 10 0 1 0 1 Using Inhibiting terms 00 01 11 10 00 1 0 1 1 01 1 0 0 1 11 d 0 d d 10 0 1 d 1 HOMEWORK: P231 4.14, 4.18,4.55,4.59

  32. 1 t X 1 t Z F 1 t Y 1 t 1 t 1 t 1 t 4.4 Timing Hazards While At the same time If 1-glitch Static-1 hazard Static-0 hazard 0-glitch

  33. X Z F Y (Sum of products) Find the conditions for (Product of sums) 00 01 11 10 Tangency 0 1 1 0 0 1 0 1 1 0 Consensus term HOMEWORK: P232 4.19 Circuit with static-1 hazard eliminated

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