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A Novel Approach For Color Matrixing & 2-D Convolution

A Novel Approach For Color Matrixing & 2-D Convolution. By Siddharth Sail Srikanth Katrue. Introduction. Matrix multiplication to convert the data into chrominance and luminance channels. Convolution to increase the sharpness of the luminance channel.

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A Novel Approach For Color Matrixing & 2-D Convolution

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  1. A Novel Approach For Color Matrixing & 2-D Convolution By Siddharth Sail Srikanth Katrue

  2. Introduction • Matrix multiplication to convert the data into chrominance and luminance channels. • Convolution to increase the sharpness of the luminance channel. • To enhance image quality unsharp masking algorithm needs to be applied i.e. subtracting blurred version of image from image itself.

  3. 9 Multipliers model • Register banks • To delay the signal propagation • 9 Multipliers • Adders • For convolution • Multiplexers • To select different sets of multiplier constants

  4. Multiplication Mode

  5. Convolution mode

  6. Ripple Carry Adder • Bottom up design methodology. • Here output carry from previous block is fed to input carry of next block. • Initially half adder was built, using this full adder and then a 4 bit adder and then the 20 bit adder was built.

  7. Multiplier • Ripple carry array multiplier design used. • Half adders and full adders are used to combine the bit products. • Bit multiplication is done using AND gates. • Maximum delay is from the MSB to LSB.

  8. 4x4 Multiplier Structure

  9. Features • 9 multiplier model makes the following assumptions : • Speed of utmost importance • Cost of minimal importance • Lack of restrictions on the amount of area consumed • Abundant resources

  10. Simulation for 9 multiplier model

  11. Simulation for 2-D Convolution

  12. Proposed 3 Multiplier model • A 3 multiplier model is proposed making the following assumptions : • Speed of minimal importance • Cost of utmost importance • Limited amount of resources available • Reduction of the area consumed

  13. 3 Multiplier model • 3 multipliers • Register banks • Three 3:1 multiplexers • Nine 20 bit registers • 1 shift register

  14. Mode 0 =>multiplication Mode 1 =>convolution Multiplication Multiply IN_0, IN_1, IN_2 with C20, C21, C22 Multiply IN_0, IN_1, IN_2 with C20, C21, C22 Multiply IN_0, IN_1, IN_2 with C20, C21, C22 Convolution Addition of the three multiplier outputs Functioning

  15. Simulation for 3 multiplier model

  16. Results of Individual Components

  17. Top level Results

  18. Applications • Noise reduction • Image enhancement • Feature extraction • Color rendition of hard copy prints • Image restoration

  19. Future Work • Using low power components like components from arm core. • The use of pipelined logic could help realize a 3 multiplier model without sacrificing the speed obtained by the 9 multiplier model. • Using carry look ahead adder to increase speed.

  20. Thank you Dr.Hsu

  21. References • [1] K.Hsu,L.J.Luna,H.Yeh, “A pipelined asic for color matrixing and convolution”,IEEE Journal. • [2] Robert A.Frohwerk, signature analysis: A new digital field service method,Hewlett packard journal may 1977,Palo Alto,CA. • [3] Lionel J.D.Luna,kenneth A. parulski IEEE member, A systems approach to custom VLSI for a digital color imaging system. • [4] P.A. Ruetz and R.W. Broderson, Architectures and Design Techniques for Real-time Image-processing IC's, IEEE Journal of Solid-state Circuits, vol. sc-22, no. 2, April 1987. • [5]W. Wesley Peterson and E. J. Weldon, Jr., Error- Correcting Codes (2nd ed.), 1972, The MIT Press, Cambridge, Massachusetts, 1972, • [6] N. Takagi, H. Yasuura, and S. Yajima, “High-speed VLSI multiplication algorithm with a redundant binary addition tree,” IEEE Trans. Comput., vol. C-34, pp. 789-796, Sept. 1985. • [7] J. E. Vuillemin, “A very fast multiplication algorithm for VLSI imple- mentation,” Integration, VLSI J., vol. 1, pp. 39-52, Apr. 1983. • [8] S. Kawahito, K. Mizuno, and T. Nakamura, “Multiple-valued current- mode arithmetic circuits based on redundant positive-digit number representations,” in Proc. Int. Symp. Multiple-Valued Logic, Victoria, Canada, May 1991, pp. 330-339.

  22. References • [9] M. R. Santoro and M. A. Horowitz, “SPIM: A pipelined 64 x 64-bit iterative multiplier,” IEEE J . Solid-state Circuits, vol. SC-24, Apr. 1989. • [10] N. Takagi, H. Yasuura, and S. Yajima, ‘(High Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree, ” IEEE Trans. Comp., C-34, pp. 789-795, 1985. • [11] M. Kameyama and T. Higuchi, “Design of radix-4 signed-digit arith- metic circuits for digital filtering,” in Proc. Int. Symp. Multiple-Valued Logic, June 1980, pp. 272-277. • [12] L. P. Rubinfield, “A proof of the modified Booth’s algorithm for multiplication,” IEEE Trans. Comput., vol. C-24, pp. 1014-1015, Oct. 1975. • [ 13] K. Hwang, Computer Arithmetic-Principle, Architecture and Design. New York: Wiley, 1979. • [14] R. K. Montoye, P. W. Cook, E. Hokenek, and R. P. Havreluk, “An 18 ns 56-bit multiply-adder circuit,” in Dig. Tech. Papers, Int. Solid-State Circuits Conf, WPM 3.4, Feb. 1990, pp. 4 6 4 7 .

  23. Questions ?

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