Soft Error with Reliability and Testability

1. Soft Error with Reliability and Testability Speaker : Chia-ChiLin Advisor : Chun-Yao Wang 2008.11.6 Department of Computer Science National Tsing Hua University, Taiwan 1

2. Outline Introduction Our approach Future work 2

3. Introduction A soft error is a signal which is temporary wrong and can be seen at the outputs Use RAR (or IRRA) to increase circuits’ reliability under testability and area constraints Previous works Chuang-Chi’s work-A Statistic-based Approach to Testability Analysis Chun-Chi’s work – Rewiring Using IRredundancy Removal and Addition 3

4. Flow chart Start Finish Simulation-based estimation no yes Can’t be better in several times Find a target wire Re-simulate the rewiring parts yes Circuit reliability get better Decide the destination tobe rewired Local rewriting no

5. Outline Introduction Our approach Simulation-based reliability and testability estimation UseIRRA to rewire the circuit and increase reliability Local Rewriting Flow chart Future work 5

6. Simulation-based estimation • Controllability • con1(g): ones( sig(g) ) / K • con0(g): zeros( sig(g) ) / K • Observability • obs(g): ones( ODCmask(g) ) / K • Testability • test1(g): ones( sig(g) & ODCmask(g) ) / K • test0(g): ones( ~sig(g) & ODCmask(g) ) / K • MEI(g) • perr0(g)test1(g)+perr1(g)test0(g)

7. Simulation-based estimation • Simulation-based estimation flow • Step 1.Simulate signaturevalue • Step 2. Levelize the circuit and sort the re-convergent wire in decrease levelorder • Step 3.Calculate ODC masking • Step4. In step 3,re-simulate re-convergent parts • Step5.Caculate the testability and MEIof each node

8. Estimation result

9. Runtime • Result:

10. Conclusion • Perr0 and perr1 are still unknown • perr0(g)test1(g)+perr1(g)test0(g) • Can not verify the correction of our method because the circuit structures are different • Run time is worse than Anser • Use too many pointers • Reconvergent fanouts’ evaluations are time consuming

11. Outline Introduction Our approach Simulation-based reliability and testability estimation UseIRRA to rewire the circuit to increase reliability Local Rewriting Future work 11

12. Our rewiring schemes • Rewiring flow • Step 1. Decide all destinations in the network and compute the rectification networks for each gn • Step 2. In step 1, we can also decide SMAs’ types • Irredundant SMA • Redundant SMA • Semi-redundant SMA • Step 3. Choose the destination lead tothe largest reliability improvement and rewire the circuit

13. Decide all destinations 0 D’:+ab’ab’ce’ e g8 O1 c D’:+ab’ab’ce’ 1 g6 1 g7 D’:+ab’ab’c D’:+ab’ 0 b g1 D’:+ab’ g3 D’:+ab’a a 1 D’:+a g5 O2 0 0 g4 • SMA:ab’ce’ • Irredundant—ab’c • Redundant—e’ • semi-redundant g2 0 d 0 D’:+ab’

14. Choose a destination • Error masking analysis in different gate types in SIS circuits OR: gf gf and AND(SMA)s’ on set must be as similar as they can c SMA Error masking AND: gf The off-set of gf and the on-set of AND(SMA)s’ must be as similar as they can c SMA Error masking

15. Choose a destination ir:0 ir:1 ir:0 ir:1 gx 0 gx gx gx 1 0 1 ir:0 ir:1 r:1 i:0 0 D’:+ab’ab’ce’ e g8 O1 c D’:+ab’ab’ce’ g6 g7 D’:+ab’ab’c D’:+ab’ b g1 g3 D’:+ab’ D’:+ab’a a D’:+a g5 O2 0 g4 g2 d D’:+ab’

16. Outline Introduction Our approach Simulation-based reliability and testability estimation UseIRRA to rewire the circuit to increase reliability Local Rewriting Future work 16

17. Rewriting • DAG-Aware AIG Rewriting • A Fresh Look at Combinational Logic Synthesis • Alan Mishchenko, SatrajitChatterjee, Robert Brayton • Department of EECS, University of California • AIG-And-Inverter Graph • DAG-Directed Acyclic Graph

18. Rewriting • Use of 4-input cuts instead of two-level subgraphs • Restricted rewriting to preserve the number of logic levels • Variations of AIG rewriting that look at larger subgraphs and attempt to reduce the delay • Experimental tune-up for logic synthesis applications

19. Rewriting • Using 4-input cuts • Φ(n) ={{n}} ∪ {u ∪ v | u ∈ Φ(a), v ∈ Φ(b), |u ∪ v| ≤ 4} • NPN equivalent • F = ab + c and G = ac + b (O) • F = ab + c and G= ab (X) • Hash table

20. Rewriting • Simple examples of AIG rewriting • zero-cost replacements Node #: 3 Node #: 2 a a a c b c b Node #: 4 Node #: 3 a a a c b c b a a b c

21. Rewriting • Result

22. Rewriting for reliability • Use rewriting for local densely congregate nets • IRRA • rewriting add ac may be redundant ac may be redundant a b a,c is redundant b c a c SER decrease ! a a a c b c a b a b c

23. Conclusion • IRRA may cause some nodes whichin the original circuit become redundant • Rewriting can find the nodes already inside the circuit to do zero-cost replacements • Using rewriting in local parts can reduce area and reliability at the same time, it can even avoid the loading of IRRA

24. Outline Introduction Our approach Future work 24

25. Future work • Programming • Study more papers