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Soft Error Rates with Inertial and Logical Masking Fan Wang* Vishwani D. Agrawal

Soft Error Rates with Inertial and Logical Masking Fan Wang* Vishwani D. Agrawal vagrawal@eng.auburn.edu. Department of Electrical and Computer Engineering Auburn University, AL 36849 USA. 22 th IEEE International Conference on VLSI Design.

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Soft Error Rates with Inertial and Logical Masking Fan Wang* Vishwani D. Agrawal

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  1. Soft Error Rates with Inertial and Logical Masking Fan Wang* Vishwani D. Agrawal vagrawal@eng.auburn.edu Department of Electrical and Computer Engineering Auburn University, AL 36849 USA 22 th IEEE International Conference on VLSI Design *Presently with Juniper Networks, Inc. Sunnyvale, CA VLSID'2009

  2. Outline • Background • Problem Statement • Analysis • Results and Discussion • Conclusion VLSID'2009

  3. Motivation for This Work • With the continuous downscaling of CMOS technologies, the device reliability has become a major bottleneck. • The sensitivity of electronic systems can potentially become a major cause of soft (non-permanent) failures. • The determination of soft error rate in logic circuits is a complex problem. It is necessary to analyze circuit reliability. However, there is no comprehensive work that considers all the factors that influence the soft error rate. VLSID'2009

  4. Strike Changes State of a Single Bit 1 0 Definition from NASA Thesaurus: “Single Event Upset (SEU): Radiation-induced errors in microelectronic circuits caused when charged particles [also, high energy particles] (usually from the radiation belts or from cosmic rays) lose energy by ionizing the medium through which they pass, leaving behind a wake of electron-hole pairs”. VLSID'2009

  5. p p n n p n n p n p n Earth’s Surface Cosmic Rays Source: Ziegler et al. • Neutron flux is dependent on altitude, longitude, solar activity etc. VLSID'2009

  6. Problem Statement • Given background environment data • Neutron flux • Background energy (LET*) distribution *These two factors are location dependent. • Given circuit characteristics • Technology • Circuit netlist • Circuit node sensitive region data *These three factors depend on the circuit. • Estimate neutron caused soft error rate in standard FIT** units. *Linear Energy Transfer (LET) is a measure of the energy transferred to the device per unit length as an ionizing particle travels through material. Unit: MeV-cm2/mg. **Failures In Time (FIT): Number of failures per 109 device hours VLSID'2009

  7. Measured Environmental Data • Typical ground-level neutron flux: 56.5cm-2s-1. • J. F. Ziegler, “Terrestrial cosmic rays,” IBM Journal of Research and Development, vol. 40, no. 1, pp. 19.39, 1996. • Particle energy distribution at ground-level: “For both 0.5μm and 0.35μm CMOS technology at ground level, the largest population has an LET of 20 MeV-cm2/mg or less. Particles with energy greater than 30 MeV-cm2/mg are exceedingly rare.” • K. J. Hass and J. W. Ambles, “Single Event Transients in Deep Submicron CMOS,” Proc.42nd Midwest Symposium on Circuits and Systems, vol. 1, 1999. Probability density 0 15 30 Linear energy transfer (LET), MeV-cm2/mg VLSID'2009

  8. Occurrence rate Proposed Soft Error Model VLSID'2009

  9. X Y 1 Y 0 τp 2τp X Pulse Width Probability Density Propagation fX(x) Delay τp fY(y) We use a “3-interval piecewise linear” propagation model • Non-propagation, if X≤τp. • Propagation with attenuation, if τp < X<2τp. • Propagation with no attenuation, if X2τp. Where • X: input pulse width • Y: output pulse width • τp : gate input to output delay VLSID'2009

  10. Probability Transformation • Consider random variables x and y, and • Function, Y = F(X) • Given, P.D.F. of X is p(x) • P.D.F. of Y: p(x)dx = p(y)dy; p(y) = p(x)/(dy/dx) y+dy y Y = F(X) X x x+dx VLSID'2009

  11. Validation Using HSPICE Simulation CMOS inverter in TSMC035 technology with load capacitance 10fF VLSID'2009

  12. Comparing Methods VLSID'2009

  13. Experimental Results Comparison *BPTM: Berkeley Predictive Technology Model VLSID'2009

  14. More Result Comparison * The altitude is not mentioned for these data. VLSID'2009

  15. Circuit Topology and SER • Circuit topology influences the logic SER. • We have analyzed two types of circuits for different sizes, an inverter chain and a ripple carry adder. • For inverter chain, in TSMC035 technology the critical width is between 25ps and 50ps. • For ripple carry adder, the critical width may not exist. VLSID'2009

  16. Inverter Chain and SER VLSID'2009

  17. Ripple Carry Adder and SER VLSID'2009

  18. Conclusion • SER in logic and memory chips will continue to increase as devices become more sensitive to soft errors at sea level. • By modeling the soft errors by two parameters, the occurrence rate and single event transient pulse width density, we effectively account for the electrical masking of circuit. • Our research on critical width of SER for different circuit topologies may provide better insights for soft error protection schemes. VLSID'2009

  19. References [1] R. R. Rao, K. Chopra, D. Blaauw, and D. Sylvester, “An Efficient Static Algorithm for Computing the Soft Error Rates of Combinational Circuits,” Proc. Design Automation and Test in Europe, pp. 164-169, 2006. [2] R. Rajaraman, J. S. Kim, N. Vijaykrishnan, Y. Xie, and M. J. Irwin, “SEAT-LA: A Soft Error Analysis Tool for Combinational Logic," Proc. 19th International Conference on VLSI Design, 2006, pp. 499-502. [3] G. Asadi and M. B. Tahoori, “An Accurate SER Estimation Method Based on Propagation Probability,” Proc. Design Automation and Test in Europe Conf, 2005, pp. 306-307. [4] M. Zhang and N. R. Shanbhag, “A Soft Error Rate Analysis (SERA) Methodology,” Proc.IEEE/ACM International Conference on Computer Aided Design, 2004, pp. 111-118. [5] T. Rejimon and S. Bhanja, “An Accurate Probabilistic Model for Error Detection,” Proc. 18th International Conference on VLSI Design, 2005, pp. 717-722. [6] J. Graham, “Soft Errors a Problem as SRAM Geometries Shrink,” http://www.ebnews.com/story/OEG20020128S0079, ebn, 28 Jan 2002. [7] W. Leung, F.-C. Hsu and M. E. Jones, “The Ideal SoC Memory: 1T-SRAMTM,” Proc. 13th Annual IEEE International ASIC/SOC Conference, pp. 32-36, 2000 [8] Report, “Soft Errors in Electronic Memory-A White Paper," Technical report, Tezzaron Semiconductor, 2004. [9] F. Wang, “Soft Error Rate Determination for Nanometer CMOS VLSI Circuits,” Master’s Thesis, Auburn University, Electrical and Computer Engineering, May 2008. VLSID'2009

  20. Thank You . . . VLSID'2009

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