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Processor Design: Datapath and Control Signals Overview

This presentation provides an overview of datapath design and control signals in processor design. It covers basic functional units, instruction sequencing, operations on data in registers, and memory. The content includes single-cycle and multicycle implementation schemes with relevant diagrams and tables.

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Processor Design: Datapath and Control Signals Overview

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  1. Processor Design Datapath and Design

  2. All tables and diagrams in this presentation are from: D. Patterson and J. Hennessy, Computer Organization and Design: The Hardware/Software Interface, Third Edition (The Morgan Kaufmann Series in Computer Architecture and Design), Morgan Kaufmann, 2002.

  3. Datapath

  4. Basic Functional Units

  5. Instruction Sequencing

  6. Operations on Data in Registers

  7. Registers and Memory

  8. Simple Implementation Scheme Single cycle Implementation

  9. ALU Conttrol

  10. Control Signals

  11. R-format and I-format Instructions

  12. Control Signals and Instruction Opcode

  13. Control Function

  14. Multicycle Implementation

  15. Intstruction fetch IR <= Memory[PC]; PC <= PC+4 IR <= Memory[PC]; PC <= PC+4

  16. IorD= 0 MemRead= 1 IRWrite= 1 IR <= Memory[PC];

  17. PCSource= 01 PCWrite= 1 ALUOp= 00 ALUSrcB= 01 ALUSrcA= 0 PC <= PC+4

  18. Intstruction decode/register fetch A <= Reg[ IR [25:21]]; B <= Reg[ IR [20:16] ]; ALUOut <= PC + ( SignExt( IR[15:0] ) << 2 ) A <= Reg[ IR [25:21]]; B <= Reg[ IR [20:16] ]; ALUOut <= PC + ( SignExt( IR[15:0] ) << 2 )

  19. A <= Reg[ IR [25:21]]; B <= Reg[ IR [20:16] ];

  20. ALUOp = 00 ALUSrcB = 11 ALUSrcA = 0 ALUOut <= PC + ( SignExt( IR[15:0] ) << 2 )

  21. R-type instruction ALUOut <= A op B Reg[ IR[15:11] ] <= ALUOut ALUOut <= A op B Reg[ IR[15:11] ] <= ALUOut

  22. ALUOp = ?? ALUSrcB = 0 ALUSrcA = 1 ALUOut <= A op B

  23. RegWrite = 1 MemtoReg = 0 RegDst = 1 Reg[ IR[15:11] ] <= ALUOut

  24. Load instruction ALUOut <= A + SignExt(IR[15:0]) MDR <= Memory[ALUOUT] Reg[IR[20:16] ] <= MDR ALUOut <= A + SignExt(IR[15:0]) MDR <= Memory[ALUOUT] Reg[IR[20:16] ] <= MDR

  25. ALUOp = 00 ALUSrcB = 10 ALUSrcA = 1 ALUOut <= A + SignExt(IR[15:0])

  26. IorD =1 MemRead =1 RegWrite =1 MemtoReg =1 RegDst = 0 MDR <= Memory[ALUOUT] ; Reg[IR[20:16] ] <= MDR

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