Peter Göttlicher , DESY For CALICE collaboration TWEPP 2012 Oxford , September 20 th , 2012

1. Simulations and Measurements for a Concept of Powering CALICE-AHCALat a Train-cycled Accelerator Peter Göttlicher, DESY For CALICE collaboration TWEPP 2012 Oxford , September 20th, 2012

2. Outline • Introduction: ILC, ILD, AHCAL for CALICE • Motivation for power cycling • Building blocks for power cycling • Summary

3. Introduction Accelerator and Detector for e+e- ILC: International Linear Collider e+e- collider with 0.5 -1 TeV ILD: International Large Detector e+e- needs precise detectors Concept: Particle flow algorithm e+ Collision point with detectors e- Bunches arrives as trains 1ms long trains, 199ms break, …. bunch to bunch 337ns • Technology: • High granularity calorimeters • e.g. CALICE-AHCAL-barrel Option:For factor 100 by switching off the fast analogue electronics for 99.5% of the time Low power per channel: 40µW/channel can be reached by power cycling Need

4. Introduction AHCAL: Analog-Hadron- CALorimeter for ILD Sampling sandwich with 48 layers each 3 mm scintillator + 2.5 mm electronics, infrastructure +12 mm stainless steel Scintillator tiles with SiPM readout 3cm ASIC’s for - analogue signals, - local storage while train - ADC’s - data transfer Plugged to the back of a Readout board 12 x 12 tiles 36x36 cm2 Interconnects with flex foils for signals, GND and power Layer: composed out of 3 cassettes: 2600 channels Control electronics and power connections Cassette: 2.2m long structures: 864 channels

5. Motivation Motivation: Power Cycling to avoid active Cooling Mechanical design constraint: - No cooling within calorimeter for homogeneity and simplicity - Cooling only at service end No dependence on r: bad conduction in a sandwich j : symmetry Tn and tn scales with the second power of the length • Heat • Electronics with • 1% power cycle • 25µW/channel • SiPMIdark • +15µW/channel • Need • Power cycling • To keep heat up below 0.50C Solution: Parabel + Fourier terms 0.3 Z=0m 0.2 Temperature increase [K] Z0=2.2m 0.1 0.0 0.0 0.5 1.0 1.5 2.0 z = Position along beam axis [m]

6. Building blocks Building Blocks for the Power System DAQ is Optical: No issue for EMI 4. Power supply 1. Planes with scintillators and SiPM’s, ASIC’s and PCB’s without cooling 3. cable 2. End of layer electronics with cooling

7. Building blocks ASIC for fast SiPM Signals consuming Low Power L. Raux et al., SPIROC Measurement: Silicon Photomultiplier Integrated Readout Chips for ILC, Proc. 2008 IEEE Nuclear Science Symposium (NSS08) • Functional tasks of the ASIC: • Amplify signals from 36 SiPM’sand generate self trigger • Store identified signals: 16 per train and SiPM: capacitor pipeline • Digitize • Multiplexed data transfer, daisy-chained ASIC’s Amp. Digital data transfer ADC 0.5% needed SiPM ASIC: SPIROC-2b RAM Algorithm for power cycling: The ASIC switches the current of the functional blocks OFF. until now no control of the slope. ASIC gets supplied all the time with voltage…. No dis-/charge of C’s PCB electronics and instruments stabilize the voltage all the time Bunches from collider (ILC/CLIC): A train every 200ms >20µs ON before train Fast amplifiers: 1ms ADC’s 3.2ms 1µs Common analogue parts, e.g. DAC’s, C-pipeline Digital control: 150ms

8. Building blocks ASICas current switch Measurements: - Inductive current probes Slow: DC – 5MHz Fast: 30MHz-3GHz - Setup: ASIC+ capacitors on a PCB - Expectation is ~ 1mA/channel ~40mA/ASIC, summed over all pins 13mA/pin, OK. Measured currents at the pre-amplifier-supply of ASIC Current/pin [mA/pin] Slow probe at 1 of 3 pins Time after switch [µs] One of the GND-pins 30mA/pin Fast probe Voltage pin (1 of 3) for preamplifier • System has to deal with: • EMI: electromagnetic interference • 5Hz from train repetition to few 100MHz • 2.2A for a layer, 3.4kA for AHCAL-barrel -20 0 20 40 60 [ns] time

9. Building blocks Electro Magnetic Interference in a Power Cycled System • Reference ground: • Need good definition • Any induced/applied current produces voltage drops • Separation between reference / power return / safety • or controlling currents • and keeping currents within “own” volume and instrumentation return reference Safety. PE • Current loops • To do: • Controlling return currents • Keeping loops small • Avoid overlapping with • foreign components. • Capacitive coupling • To do: • Keep common mode voltage stable • Guide induces currents to source • Keep GND-reference closer • than foreigns Guideline: Avoiding emission avoids in most cases picking up of noise

10. Building blocks Keeping the high Frequencies local Simulation model: “two diomensional delay line” 36 x 36 cm PCB with scintillators, SiPM’s, LED 144mA switched current Part of a thin cassette between absorber layer of HCAL 1cm2 0.7ns Layer structure of PCB: GND dPCB= 50-60µm Vsupply GND Well known by geometry: Capacitance: parallel plates Inductivity: 1-dim. delay-line • One gets • Athin PCB • A good high frequency capacitor 60pF/cm2 • Short traces to via to maintain the performance

11. Building blocks Voltage for ASIC stabilized by local discrete Capacitors Capacitors mounted to the 36x36cm2 PCB Simulation of voltage induced by current ASIC is supported over wide frequency range with Z< 0.1W 144mA generates <20mV Oscillations are dumped for wide frequency range with phase ¹ ±900 Trust in simulation: - <1.5GHz=(1/10) granularity - No resistive behavior of ASIC is included. That over estimates the resonances at high frequencies Result: - Locally good for > 10kHz - Additional effort < 10kHz 100 W Ceramics X7R 10 W Murata, 100nf Murata, 1nf Murata, 10nf Tantalum, AVX, 33µF Murata, 2.2nf PCB, alone 1 W Impedance Z=|U|/|I| 0.1 W Total: 12 Tantal/4 ASIC’s + 17 ceramics + PCB 0.01 W 900 Coil like U to I phase shift 00 Capacitor like -900 1GHz 1MHz 1kHz Frequency PCB-layer Tantal Dominated by: ceramic

12. Building blocks Phase variations 100MHz-1GHz Resistor can dump resonant behavior Simulation 16´ 1.6W Each AC-coupled with real 100nF Reality - Not on the boards - No negative effects seen - ASIC’s do it themselves? - Easy for next generation to be safe. 10 Granularity Limit of simulation Only PCB and C’s Additional R-C’s 1 0.1 Impedance [Ohm] 0.01 +900 00 phase -900 G Frequency [Hz] VCC 1.6W Real C: 100nF Simulation: L-R-C

13. Building blocks Low frequency charge storage for < 10kHz At end of layer, there is a bit of - space - cooling C2 C3 Concept: - Charge for the train stored in a capacitor C2 - Voltage drop allowed ~ 0.6V - Fast voltage regulator - Charge for faster reaction is within the distributed capacitors + C3 C2 = 3.4mF bank of few Tantal a voltage regulator with external FET > 2A C3+distributed = 2mF

14. Building blocks Voltage at ASIC: Measurement Reduced test setup: Control board, 1 interconnect, 1 board Definition of GND-point: - good for keeping sensitive SiPM’s stable - single connection to reduce currents in GNDPE system parasitic C=13nF 2m2/Layer 1.3mm distance Stainless steel absorber = GNDPE GNDelectronics Voltage step: - Measured 4mV, 400ns - Extrapolate to full system < 80mV at far end OK for operation, over-,undervoltage, time, … Induces current into GNDPE, if step is on GNDelectronics < 2 mA per layer Large amount of steel 4mV Default setup Supplyvoltage of ASIC (AC-component) [mV] Tantalum moved to control board Power on Command, step in IASIC Tantalum taken away Control electronics for layer Time [ns] Þ OK, even with extrapolation to 1500 layers low? Investigations of reason and improvements possible, to be watched

15. Building blocks Integrating to Infrastructure 70pF/m from cable to support ASIC as switched current sink Not simulated • Impact of cable • is a combination of choices: • Input filter: R=10W, C=1mF • reasonable mechanical size • EMI better t=100ms • Power supply behavior here - no capacitance to PE • - ideal V-source • Mechanical integration and galvanic isolation • per (group or) layer • and pair of wires for it 50m cable, 1mm2, on a cable support Current induced into GNDPE nA 0 -40 -80 -120 -160 Current per layer Simulation of cable 0 1 2 3 4 5 [ms] 6 time With 1500 layers of AHCAL: IPE=120mA Really small, but not all parasitic effects! Don’t be too reluctant in EMI-rules

16. Building blocks Integration of parasitic parameters of infrastructure Real Tantalum-C’s Power supply: Cto chassis(Toellner) Cable above metal support Inductance to support 1cm Parasitic LC (only return): 0.5m Current switch Current switch Parasitic elements increases currentpp a factor 5000 0 16µs 0 Slope is dis-/recharge during train Current in PE [A] Very small amplitude oscillation -0.5m -10µ 0ms 1ms 0µs 50µs Time after current switch Need: - Reasonably done infrastructure, e.g. small L’s, C’s - Electronics (e.g. p-filter) reducing sensitivity

17. Building blocks Current in Supply Cable Reduced test setup: Control board, 1 interconnect, 1 board, Short cable to laboratory supply Preamplifiers ON ADC’s ON Work bench settings Without input filter with input filter t=10ms Current per 1/18 layer in supply cable [mA] Input filter important to lower amplitude fluctuations and remaining frequencies within cable Important: EMI-crosstalk to others Frequencies are low Electronics like to have larger t to smoothen further Û Mechanics easier in service-hall Control electronics for layer

18. Consequences per power supply • Multichannel systems • - to keep supply/return currents near, • not using metal infrastructure to distribute • Floating per channel: Individual voltage drops • Low ripple: 5-10(20) mVpp • It is not too exotic, • But for 1500 layers , • best individual, • or in small geometrical nearby groups • Need a well adopted system. • On the market • are developments (partially) driven by research • CAEN, ISEG, WIENER and ?????? • ? • DC/DC-converters • Floating • Magnetic field • Low ripple. • Pulsed load • AHCAL • - has less stringent cable • requirements, • - not really needed. • - Multi-wire cables are an • option • Others might profit To far in the future for a survey ordedicated developments

19. Status Work with single board and not 6 in a chain Performance check with single photon detections in SiPM’s • Resolution is maintained • To be worked on: • Baseline shift, but seen also at other operations(next generation of ASIC) • Longer time to stabilize than expected: ~200µsec • - PCB or ASIC? • - Voltages are settling faster • - Wouldn’t be great factor in power Without Power pulsing 0 1 2 3 photons With Power pulsing 0 1 2 3 photons

20. Summary • Detectors for Linear Colliders requires many channels with low power • Train structure allows 99% time to be OFF: Factor 100 in critical regions • Coherent fast switching ON/OFF of high current: CALICE-AHCAL: 2.2A*layers : 3.4kA for the barrel 5Hz to few 100MHz • System aspects at local design - Local defined return-paths for current - Local charge storage for wide frequency ranges that keeps - impedances small - currents leaving a defined volume small and slowly rising/falling • System aspects within the infrastructure Lower frequency part is partially on the cables and power supplies. Good integration of power supplies and cables needed. • Simulation leaves many parasitic effects out – first integrations done That usually underestimates the high frequency EMI-disturbance …. Therefore planning a conservative approach. • Experimental setups, integration, wishlists into ILD to be continued