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Design and Implementation of VLSI Systems (EN1600) Lecture 25: Datapath Subsystems 1/4

Design and Implementation of VLSI Systems (EN1600) Lecture 25: Datapath Subsystems 1/4. Prof. Sherief Reda Division of Engineering, Brown University Spring 2008. [sources: Weste/Addison Wesley – Rabaey/Pearson]. Adders Multipliers Comparators Counters Shifters. Datapath Subsystems.

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Design and Implementation of VLSI Systems (EN1600) Lecture 25: Datapath Subsystems 1/4

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  1. Design and Implementation of VLSI Systems (EN1600) Lecture 25: Datapath Subsystems 1/4 Prof. Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Weste/Addison Wesley – Rabaey/Pearson]

  2. Adders Multipliers Comparators Counters Shifters Datapath Subsystems

  3. Adders Addition is the most commonly used arithmetic operation → could be speed limiting → optimization of the adder is of the utmost importance

  4. A N-bit carry-ripple adder can be constructed by cascading 1-bit FA Worst case delay linear with the number of bits td = O(N) tadder = (N-1)tcarry + tsum Goal: Make the fastest possible carry path circuit

  5. Full adder Boolean equations S can be factored to reuse the Co term

  6. An implementation that requires 28 transistors

  7. Note Problems: • Ci is connected to the transistor closest to the output • Large area • Tall transistor stacks • Large intrinsic capacitance for Co Problems with the design

  8. Self-dual property of FAs • A full adder receiving complementary inputs produce complementary outputs • B. An inverting full adder receiving complementary inputs produce true outputs • Self duality enables two optimizations: • PGK mirror FA • Faster ripple carry adder

  9. For a full adder, define what happens to carry Generate: Cout = 1 independent of C G = A • B Propagate: Cout = C P = A  B Kill: Cout = 0 independent of C K = ~A • ~B A. PGK mirror FA design

  10. V DD V A V DD DD A B A C B B B i Kill "0"-Propagate A C i C o S C i C A i "1"-Propagate Generate A B A A B C B i B A. The mirror adder • Still need two inverters to generate Co and S • Less area • Shorter stacks • Less intrinsic capacitance

  11. A. Mirror adder stick diagram

  12. Even cell Odd cell A B A B A B A B 0 0 1 1 2 2 3 3 C C C C C i ,0 o ,0 o ,1 o ,2 o ,3 FA FA FA FA S S S S 0 1 2 3 B. Minimize critical path (carry) by reducing the number of inverters along the path , , , , • FA’ is a FA without the inverter in the carry path

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