Chapter 10 Digital CMOS Logic Circuits

1. Chapter 10Digital CMOS Logic Circuits • 10.1 Digital circuit design : An overview • 10.2 Design and performance analysis of the CMOS inverter • 10.3 CMOS logic gate circuits • 10.4 Pseudo- NMOS logic circuits

2. 10.1 Digital circuit Design : An Overview10.1.1 Digital IC technologies and logic circuit familiesFig. 10.1 Digital IC technologies and logic circuit families

3. CMOS • Replaced NMOS (much lower power dissipation) • Small size, ease of fabrication • Channel length has decreased significantly (as short as 0.06 µm or shorter) • Low power dissipation than bipolar logic circuits ( can pack more) . • High input impedance of MOS transistors can be used to storage charge temporarily (not in bipolar) • High levels of integration for both logic (chapter 10) and memory circuits (chapter 11) . • Dynamic logic to further reduce power dissipation and to increase speed performance .

4. Bipolar • TTL (Transistor-transistor logic) had been used for many years . • ECL (Emitter –Coupled Logic) : basic element is the differential BJT pair in chapter 7 . • BiCMOS : combines the high speed of BJT’s with low power dissipation of CMOS . • GaAs : for very high speed due to the high carrier mobility . Has not demonstrated its potential commercially .

5. Features to be Considered • Interface circuits for different families • Logic flexibility • Speed • Complex functions • Noise immunity • Temperature • Power dissipation • Co$t

6. 10.1.2 Logic circuit characterizationFig. 10.2 Typical voltage transfer (VTC) of a logic inverter .

11. Fig. 10.3 Definitions of propagation delays and switching times of the logic inverter

15. Fan-In and Fan -Out • Fan-in of a gate : number of inputs . • Fan-out : maximum number of similar gates that a gate can drive while remaining within guaranteed specifications (to keep NMH above certain minimum) .

16. 10.2 Design and performance analysis of the CMOS inverter .10.2.1 Circuit structureFig. 10.4 (a) The CMOS inverter and (b) its representation as a pair of switches operated in a complementary fashion .

17. 10.2.2 Static operation

18. 10.2.2 Static operationFig. 10.5 The voltage transfer characteristic (VTC) of the CMOS inverter when QN and QP are matched

23. 10.2.3 Dynamic OperationFig. 10.6 Circuit for analyzing the propagation delay of the inverter

24. Fig. 10.7 Equivalent circuits for determining the propagation delays

42. 10.3 CMOS Logic Gate Circuits10.3.1 Basic structureFig. 10.8 Representation of a three- input CMOS logic gate

43. Fig. 10.10 Examples of pull –down networks (PDN)

46. Fig. 10.10 Examples of pull- up networks (PUN)

47. Fig. 10.11 Usual and alternative symbols for MOSFETs

48. 10.3.2 The Two – Input NOR GateFig. 10.12 A two – input CMOS NOR gate

49. 10.3.3 The Two- Input NAND GateFig. 10.13 A two-input CMOS NAND gate

50. 10.3.4 A Complex Gate