An Integrated Floorplanning with an Efficient Buffer Planning Algorithm

1. An Integrated Floorplanning with an Efficient Buffer Planning Algorithm Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen Yici Cai Chung-Kuan Cheng Jun Gu Department of Computer Science and Technology, Tsinghua University, Beijing,100084 P.R. China Department of Computer Science and Engineering,University of California, San Diego,La Jolla, CA 92093-0114,USA Department of Computer Science,Science & Technology University of HongKong

2. OUTLINE • Introduction • Problem definition • Review of Corner Block List • Dead space partition while doing the packing • Computation of possible buffer insertion sites • Experimental Results • Conclusions

3. Introduction • In deep submicron design, interconnect delay and routability have become the dominant factor: • The VLSI circuits are scaled into nanometer dimensions and operate in gigahertz frequencies • To ensure the timing closure of design, interconnects must be considered as early as possible • Buffer insertion has shown to be an effective approach to achieve timing closure. • As transistor count and chip dimension get larger and larger, more and more buffers are expected to be needed for high performance; • They cannot be placed over the existing circuit blocks • Placing a large number of buffers between circuit blocks could significantly impact the chip floorplan • Therefore, it is necessary to start buffer planning as early as possible.

4. Previous works on buffer insertion • Feasible Region -------J. Cong, T.Kong et al. • The feasible region for a buffer is the maximum region where the buffer can be located such that the target delay of the net can be satisfied. They make use of dead space and channel region between circuit blocks to insert buffers. • Independent Feasible Region and Congestion-Driven Buffer Insertion ----P. Sarkar, C. K. Koh • Net Flow Algorithm------- Tang and Wong • Multi-Commodity Flow-Based Approach -------- F.F. Dragan et al • Pre-existing buffer blocks • Make Use of Tile Graph and Dynamic Programming --- Alpert et al. • They assume that buffers be allowed to be inserted inside macro blocks and their approach will distribute buffer sites all over the layout. • Routability Driven Floorplanner-----Sham et al. • Which can estimate buffer usage and buffer resource for the congestion constraint

5. Feasible Region Feasible Region T S T (a) the 2-D feasible region Buffer is inserted in the FR S (b) the feasible region reduced by circuit blocks the 2-D independent feasible region • Sarkar and Koh gives the notion of independent feasible regions(IFR) • Each driver/buffer is modeled as a switch-level RC circuit and the Elmore delay formula is used for delay computations. • Since the feasible region will be reduced by the circuit blocks, the feasible region for buffer insertion in the packing is a very complex polygon, normally concave polygon

6. OUTLINE • Introduction • Problem definition • Review of Corner Block List • Dead space partition while doing the packing • Computation of possible buffer insertion sites • Experimental Results • Conclusions

7. Problem definition • Buffer insertion constraints • Given the timing constraints on each net, buffers should be inserted to meet the timing constraints. • The insertion of buffers should be in the dead spaces between circuit blocks. • Buffer insertion embedded in the floorplanning • Find the number and locations of buffers. • The buffer allocation is handled as an integral part in the floorplanning process. • The floorplanning methodology to produce the optimal floorplan such that the floorplan area and wire length are minimized and the buffers can be inserted in the dead spaces as much as possible.

8. The overall algorithm Packing the blocks by given solutions and partition the dead spaces into blocks Buffer planning Solution perturbation and decrease the temperature Solution evaluation No Stop annealing ? Yes Specs of blocks, nets, timing Initial Solution of annealing process Floorplanning Buffer Planning • Buffer insertion could significantly impact the chip floorplan! • Some timing constraints can not be amended only by buffer insertion!

9. OUTLINE • Introduction • Problem definition • Review of Corner Block List • Dead space partition while doing the packing • Computation of possible buffer insertion sites • Experimental Results • Conclusions

10. CBL representation d {S1,S2,...Sn} {L1,L2,...Ln} {T1,T2,...Tn} • For each block deletion • block name Si • block orientation Li • number of attached T-junction Ti d d e e a a g g c c b b f f • Sd=d  Ld=0  Td={10} • At the end of deletion • {Sn,Sn-1,…S1} • {Ln,Ln-1,…L2} • {Tn,Tn-1,…T2}

11. The Operation of CB d d The deletion of CB The insertion of CB d d e e e e a a a a g g g g c c c c b b b b f f f f • Corner block ‘d’ is vertical and it is deleted. • An attached T-junctions was pulled to the top. • Corner block ‘d’ is inserted from top. • An attached T-junctions was covered.

12. OUTLINE • Introduction • Problem definition • Review of Corner Block List • Dead space partition while doing the packing • Computation of possible buffer insertion sites • Experimental Results • Conclusions

13. Dead space in packing • Dead Space Block (DS block): The dead spaces between the circuit blocks can be partitioned into rectangles which are called dead space blocks and the buffer blocks should be packed within the range of dead-space blocks. • The buffer must be inserted within the intersection of its feasible region and a dead space block. • Partitition Rules • No overlapping between each dead space blocks; • The number of the dead space blocks should be as few as possible;

14. The dead space partition e e f f b 2 b 2 d d a a 1 1 c c (a) (b) • Based on CBL, we propose the algorithm to obtain the dead space blocks in the floorplanning while doing the packing. • The number of the dead space blocks(NDS) in CBL packing should be less than n –1, where n is the number of the blocks. • The partition method will not generate overlapping between dead space blocks 4 3 the example packing process

15. An Example e f g b d a c • Given CBL： • S=(abcdefg) • L=(010011) • T=(1 0 1 0 10) L2=0,T2=nil; CB=b; L3=1,T3=1;CB=c; L4=0,T4=0;CB=d; 5 6 L5=0,T5=1;CB=e; 3 1 2 L6=1,T6=0;CB=f; 4 L7=1,T7=10;CB=g;

16. OUTLINE • Introduction • Problem definition • Review of Corner Block List • Dead space partition while doing the packing • Computation of possible buffer insertion sites • Experimental Results • Conclusions

17. Possible insertion sites • The computation of buffer insertion sites is the most difficult and time-consuming part when doing the buffer planning. • Instead of computing the size of the dead space in each grid in the packing, we compute the intersection between the dead space blocks and the FRs in a 2-step method. • the first step is to compute the intersected blocks between dead space blocks and the bounding box of the source and sink; • the second step is to compute the overlapping between the result blocks in the first step and the region between two parallel lines which are the two edges of the FR.

18. S (a) slope is -1 (b) slope is +1 T 10 7 6 3 11 1 15 3 18 14 20 10 1 14 6 17 13 17 9 2 2 12 4 8 19 16 5 4 9 8 19 16 2 4 17 13 5 12 19 18 11 11 7 20 14 10 7 15 15 3 18 20 1 6 Possible buffer insertion sites 5 4 6 1 3 2 Possible buffer insertion sites are between grid 4 and grid 17

19. Buffer insertion sites • The number of possible insertion sites of the ith FR (NFRi) intersected with dead space should be • `NFRi ={(| GP - GQ |) | for all the dead space blocks intersected with FRi } • If NFRi = 0, then the buffer will not be placed properly since there is no available insertion sites. • The total buffer insertion probability of grid G is • PG = {sum(PGNi) | for each feasible region which has intersection with grid G}

20. Two-phase annealing • We divide the annealing process into two phases: timing optimization phase and buffer insertion phase. • In the timing optimization phase, we estimate the buffer insertion by probability budget; • If the probability of the grid is larger than the capacity, we think the buffers inserted will be too crowded thus we should take some measure to control it. • Cost = Area + p*Wire + q* Tviolations +s*B_evaluate • B_evaluate = Count{( NFRi = 0)| for all nets} + Count{( PG>R)|for all grids} • In the buffer insertion phase, we do the buffer allocation by the heuristic methods • Cost = Area + p*Wire + q* Tviolations + r*Bnot_inserted

21. OUTLINE • Introduction • Problem definition • Review of Corner Block List • Dead space partition while doing the packing • Computation of possible buffer insertion sites • Experimental Results • Conclusions

22. circuit Description blocks nets 2-pin net Value apte R Wire resistance per unit length(m) 9 97 172 0.075 C xerox Wire capacitance per unit length(fF/m) 10 203 455 0.118 Tb hp Intrinsic buffer delay(ps) 11 83 226 36.4 Ami33 Cs/Cb Sink/buffer capacitance(fF) 33 123 363 23.4 Rb/Rd Ami49 Driver/buffer output resistance() 49 408 545 180 Table 2. MCNC Benchmark Table 1. Parameter List

23. Area(mm2) Wire(mm) #Inserted B/#B #meet #violation Time(s) Test1 F1 F2 F1 F2 F1 F2 F1 F2 F1 F2 F1 F2 Xerox_1 Xerox_c 84.57 85.41 1343 1327 189/395 214/303 193 370 124 51 12 59 91.16 86.32 1424 1439 70/345 84/319 159 296 224 88 28 64 Ami33_1 Ami33_c 30.86 31.15 431.5 461.2 117/524 192/465 101 170 124 39 26 206 34.04 36.07 515.6 503.9 216/501 172/307 87 199 91 34 26 267 Ami49_1 Ami49_c 156.67 146.6 2922 2920 315/582 244/568 234 341 227 151 55 329 175.27 183.15 3471 2940 198/511 363/546 198 344 181 154 64 326 Apte_1 Apte_c 48.15 48.14 484.3 459.5 11/111 44/107 80 113 80 49 6.06 27 49.55 50.08 520.2 478.8 21/154 53/89 88 112 80 53 6.1 25 Hp_1 Hp_c 38.61 38.86 424.4 392.2 23/350 40/106 84 163 99 43 3.74 29 40.64 40.61 485.9 486.9 53/416 69/106 82 170 139 53 4.18 34 Average +0.2% -3.1% -- -- +76% -49% +509%

24. Conclusion • The buffer allocation is handled as an integral part in the floorplanning process. • Not necessarily to scan the whole packing to find the dead spaces, we can partition the dead space into blocks while doing the packing. • Instead of computing the size of the dead space in each grid, we compute the intersection between the dead space blocks and the FRs in a 2-step method. • The experiments prove the effectiveness of our approach.

25. Thank You!