Simultaneous Buffer and Interlayer Via Planning for 3D Floorplanning

1. Simultaneous Buffer and Interlayer Via Planning for 3D Floorplanning X. He, S. Dong, Y. Ma, X. Hong Tsinghua University, Beijing, China ISQED 2009

2. Outline • Introduction • Problem formulation • Preliminary • Buffer planning for 3D ICs • Algorithm improvement • Experiments • Conclusion

3. Introduction • Many techniques are employed to reduce interconnect delay. • Buffer insertion along the wires has shown to be an effective way to solve this problem. • Since buffers are implemented by transistors, they cannot be placed over the existing circuit blocks.

4. Introduction • Unlike traditional methods of buffer insertion in the 2D ICs, there are many challenges appearing in 3D ICs. • Vertical interlayer via insertion, making most of previous buffer insertion approaches cannot be applied directly in 3D ICs. • Bad via location choice will limit the allocation of buffers in each layer.

5. Introduction • A net which crosses two layers needs to insert one buffer to satisfy the timing requirement. • (a) point “a” is a bad via position, the buffer on layer 2 cannot be inserted for lacking of whitespace. • (b) the via is on a better place so that buffer can be successfully inserted and the net meets its delay constraint.

6. Problem formulation • Problem: • Buffer and interlayer via planning for 3D ICs. • Objective: • Find a floorplan, whose chip area and wirelength are minimized, while the buffers and interlayer vias can be inserted into the whitespace as much as possible, subjecting to the better timing performance.

7. Problem formulation • Inputs: • A set of modules and their size, I/O pins, net list and their timing requirements, the layers amount. • Outputs: • The coordinates and orientations of the modules, and which layer they belong to.

8. Problem formulation • The basic assumptions: • All modules are hard ones, each module has fixed size and aspect ratio. • All nets are 2-pin nets, and multi-pin nets are split into a set of source-sink 2-pin nets. • Buffers and vias can only be inserted into whitespace, and cannot be allocated inside modules. • The computation of the wirelength and timing delay during floorplanning only consider the planar wire routing in each layers.

9. Preliminary • Representation • After partitioning the modules into layers according to the area and wirelength. • Adopt the corn block list (CBL) to represent the topological relations between modules of each layer. • Because via can only be inserted into whitespace, vias between multiple layers must be inserted within the intersection of whitespaces of adjacent layers.

10. Preliminary • The floorplan of each layer is divided into a set of grids. • The vertical intersection information can be easily retrieved by checking the counterpart grids between layers. • The grid size is determined by the modules’ average size.

11. Preliminary • Independent feasible region (IFR) • IFR region of a buffer is the scopes where the buffer can be placed to satisfy the timing constraint. • The IFR of all buffers belonging to the same net do not overlap each other. • Suppose k buffers are needed for delay minimization of a net, the optimal locations of the ith buffers is:

12. Preliminary • Independent feasible region (IFR) • The width of the IFR for ith buffer (i<=k) of the net is:

13. Preliminary • Independent feasible region (IFR) • The 2D IFRs of buffers are convex rectilinear polygons with horizontal, vertical, and two parallel lines of slope +1 or -1 boundaries.

14. Buffer planning for 3D ICs • Buffer and interlayer via insertion • There are two types of nets to be considered: • The first type is those nets whose two terminals are on the same layer. • The second type is the cross multi-layer nets. • For the first type, the solution is the same as 2D buffer planning.

15. Buffer planning for 3D ICs • For the second type, the insertion process is divided into two steps: • Step1: Globally detect each layer’s buffer insertion site, while checking whether interlayer via can be inserted between different layers.

16. Buffer planning for 3D ICs • Construct a buffer connection graph. • It is used to demonstrate the possible insertion position of each buffer and interlayer via in the net’s every crossing layers.

17. Buffer planning for 3D ICs • The point in column j of row i represents the jth buffer can be successfully inserted in layer i. • The edge connecting two points from different rows represents it can insert vias within intersection whitespace blocks between layers. • Only the points from adjacent columns can be connected.

18. Buffer planning for 3D ICs • Step 2: Find a path from the source to the sink, making sure it passes k buffers in order. • If the adjacent buffers are from different layers, interlayer vias are needed to be inserted.

19. Buffer planning for 3D ICs • Whitespace redistribution • In order to get high success insertion rate of buffer and interlayer via. • Horizontal redistribution and vertical redistribution.

20. Buffer planning for 3D ICs • Whitespace redistribution • First, construct its horizontal constraint graph. • Calculate all modules’ max right moveable distance. • Breadth-First Traversal which starts from T and end at S.

21. Buffer planning for 3D ICs • Whitespace redistribution • MRMD[i]: module i’s max right moveable distance. • RAdjacent[i]: right adjacent modules of module i. • Weight(i→j): the distance from module I to module j. • For example, MRMD[E]=Weight(E→T) = 3, MRMD[D]=MRMD[E]+Weight(D→E) = 5.

22. Buffer planning for 3D ICs • Whitespace redistribution • If the capacity of left side space in the room of current visiting module is not enough, it will transfer the “expand to right” requirement to its right side space of the same room. • If the right side space is not big enough, it will transfer the “expand to right” requirement to all its right side adjacent modules.

23. Buffer planning for 3D ICs • Summary on buffer and interlayer via planning

24. Algorithm improvement • Solution Perturbation • After partitioning, randomly choose a layer to perturb in iteration of annealing process. • Modules are not allowed to exchange between layers. • Three-phase Annealing Process • Area optimization phase • Timing optimization phase • Buffer and interlayer via planning phase

25. Algorithm improvement • Three-phase Annealing Process • Area optimization phase: optimize every layer’s area respectively. • Timing optimization phase: the number of timing violation nets can be reduced as many as possible. • Buffer and interlayer via planning phase:

26. Experiments

27. Experiments

28. Conclusion • This paper has addressed the issue of simultaneous buffer and interlayer via planning which is new for 3D.