ECE 3110: Introduction to Digital Systems Chapter 5 Combinational Logic Design Practices

1. ECE 3110: Introduction to Digital SystemsChapter 5Combinational Logic Design Practices X-OR gates and Parity circuits Comparators Adders, subtractors, ALUs

2. Previous class • Building blocks • Encoders/priority encoders • Three state buffers/inverters • Multiplexers/demultiplexers

3. Exclusive OR and Exclusive NOR Gates • XOR : • XNOR : • Truth Table : XOR X Y XOR XNOR 0 0 0 1 0 1 1 0 1 0 1 0 1 1 0 1 XOR X F Y X F Y

4. XOR and XNOR Symbols • Equivalent Symbols of XOR gate • Equivalent Symbols of XNOR gate Any 2 signals (inputs or outputs) may be complemented without changing the resulting logic function

5. SSI XOR and XNOR • 74x86 : 4 XOR gates • 74x266: 4 XNOR gates with “open collector” or “open drain” output

6. XOR Application: Parity Circuit • Odd Parity Circuit : The output is 1 if odd number of inputs are 1 • Even Parity Circuit : The output is 1 if even number of inputs are 1 • Example : 4 bit Parity Circuit : Daisy-Chain Structure Tree structure Input : 1101 Odd Parity output : 1 Even Parity output: 0 I0 I0 EVEN I1 EVEN I1 I2 ODD ODD I2 I3 I3

7. MSI Parity Circuit : 74x280

8. Parity-Checking Application:memory

9. Comparators • Compares Two binary words and indicate if they are equalMagnitude Comparators : Comparator A OUTPUT B A=B A Comparator A>B B A<B

10. 4-bit comparator EQ_L Equality Comparators • 1-bit comparator

11. General structure of an iterative combinational circuit

12. Multibit Iterative Comparator

13. MSI Comparator : 74x85 • 4 bit comparator • 3 outputs : A=B, A<B, A>B • 3 Cascading inputs • Functional Output equations : (A>B OUT)= (A>B)+(A=B).(A>B IN) (A<B OUT)= (A<B)+(A=B).(A<B IN) (A=B OUT)= (A=B).(A=B IN) • Cascading inputs initial values : (A=B IN) =1(A>B IN) =0(A<B IN) =0 74x85 A<BIN A<BOUT A=BIN A=B OUT A>BIN A>BOUT A0 B0 A1 B1 A2 B2 A3 B3

14. 8 bit Comparator +5V 74x85 74x85 A<B A<BIN A<BOUT A<BIN A<BOUT A=B A=BIN A=B OUT A=BIN A=B OUT A>B A>BIN A>BOUT A>BIN A>BOUT A0 A0 A4 A0 B0 B0 B4 B0 A1 A1 A5 A1 B1 B1 B5 B1 A2 A2 A6 A2 B2 B2 B6 B2 A3 A3 A7 A3 B3 B3 B7 B3 Least Significant bits Most Significant bits

15. 8-bit Magnitude Comparator

16. Other conditions

17. Adders/Subtractors • Half Adder • Full Adder • Ripple Adder • Full Subtractor • Ripple Subtractor • Adder/Subtractor Circuit ECE311 Ch5

18. Half Adder: adds two 1-bit operands • Truth table :X Y HS=(X+Y) CO0 0 0 00 1 1 01 0 1 01 1 0 1 X H S Y CO ECE311 Ch5

19. X Y Cin S Cout 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 Full Adders: provide for carries between bit positions • Basic building block is “full adder” • 1-bit-wide adder, produces sum and carry outputs • Truth table: S is 1 if an odd number of inputs are 1. COUT is 1 if two or more of the inputs are 1. Recall: Table 2-3, pp32

20. Full-adder circuit

21. Ripple adder • Speed limited by carry chain • Faster adders eliminate or limit carry chain • 2-level AND-OR logic ==> 2n product terms • 3 or 4 levels of logic, carry lookahead

22. 74x2834-bit adder • Uses carry lookahead internally

23. 16-bit group-ripple adder

24. Subtraction • Subtraction is the same as addition of the two’s complement. • The two’s complement is the bit-by-bit complement plus 1. • Therefore, X – Y = X + Y’ + 1

25. Full subtractor = full adder, almost • X,Y are n-bit unsigned binary numbers • Addition : S = X + Y • Subtraction : D = X - Y = X + (-Y) = = X+ (Two’s Complement of Y) = X+ (One’s Complement of Y) + 1 = X+ Y’+ 1

26. Using Adder as a Subtractor • Ripple Adder can be used as a subtractor by inverting Y and setting the initial carry ( CIN ) to 1 ECE311 Ch5

27. MSI Arithmetic Logic Units (ALU ) 74x181 • ALU performs Aithmetic and Logical Functions- A , B : 4 bits inputs- S3,S2,S1,S0 : Function select- M=0 : Arithmetic operations +=Plus , - = Minus M=1 : Logical operations : += OR , . =AND • Example : Inputs FunctionsS3 S2 S1 S0 M=0 M=10 0 0 0 F= A-1+CIN F=A’0 1 1 0 F= A-B-1+CIN F=A XOR B’1 0 0 1 F= A+B+CIN F=A XOR B1 0 1 1 F=(A OR B)+ CIN F=A+B1 1 0 0 F= A+A+CIN F= 00001 1 1 1 F=A+CIN F=A S0 S1 G S2 P S3 M A=B CIN F0 A0 F1 B0 F2 A1 F3 B1 A2 COUT B2 A3 B3 ECE311 Ch5

28. Chapter Summary • Documentation Standards:- Gate symbols, Signals Active Levels, Bubble to Bubble Logic- Block diagram, Schematic Diagram, Timing Diagram. • Combinational Logic design Structures:1-Decoders : Binary Decoders, Cascading decoders, Implementing Logic Functions, Seven-Segment Decoders (HW5.18).2-Encoders : Binary Encoder, Priority Encoder, Cascading Encoders, Encoder applications.3-Three State Buffers : SSI buffers, MSI Octal Buffer , Octal Three-state Transceiver ECE311 Ch5

29. Chapter Summary • 4- Multiplexers : MUX operation, Single/Multiple outputs MUX, Expanding MUXs5- Demultiplexers : MUX/DMUX operation, Using Decoders as Demultiplexers.6- XOR and XNOR Gates: Logic Symbols, Equivalent Symbols, Parity Circuits using XOR gate, Parity Circuit application ( memory unit checking )7- Comparators : Parallel Comparators, Iterative Comparators, Cascading Comparators8-Adders : Half Adder, Full Adder, Ripple Adder, Subtractor, Ripple Adder / Subtractor Unit,Group-Ripple Adder9- Arithmetic Logic Units

30. Next… • HW #9 • Combinational circuits Design examples • Reading Wakerly Chapter 6