Partially based on Prof . Vishwani D. Agrawal lecture VLSI Testing

1. ECE 617 - Fault Testable Design Dr. Janusz Starzyk School of EECS Ohio University Athens, OH, 45701 http://www.arltesting.com/ Partially based on Prof. Vishwani D. Agrawal lecture VLSI Testing and book by S. Mourad, Y. Zorian, "Principles of Testing Electronic Systems”

2. IC Testing Machine (IC81-0444-467)

3. 3360-PVLSI Test System

4. Definition of Testing

6. Outline 0.18u VLSI silicon neurons http://www.ini.uzh.ch/node/21083 • Reliability and testing • Design Process • Verification & testing • Faults and their detection • Fault coverage • Types of tests • Test applications • Design for Test • Test economics

7. Reliability and Testing • Reliability of electronics systems is no longer limited to military, aerospace or banking • Used by almost everyone in the workplace • Applied to smaller and smaller devices • Have continually new failure modes • Reliability depending on being error free • Failures in both software and hardware • Here we concentrate on hardware

8. Test Objective • The goal over time is to reduce the cost of manufacturing the product by reducing the per-part recurring costs: • - reduction of silicon cost by increasing volume and yield, and by die size reduction (process shrinks or more efficient layout) • - reduction of packaging cost by increasing volume, shifting to lower cost packages if possible (e.g., from ceramic to plastic), or reduction in package pin count

9. Test Objective • - reduction in cost of test by: • - reducing the vector data size • - reducing the tester sequencing complexity • - reducing the cost of the tester • - reducing test time • - simplifying the test program

10. A System on a Chip

11. Verification and Testing • Testing a circuit prior to fabrication is known as design verification • Verification is certainly done at various stages of the design process • Most viable design verification is through simulation • Testing is identifying that the fabricated circuit is free from errors • Need to specify what errors testing is looking for

12. DFT Cycle

13. Test Programming

16. Types of Logic Faults

17. Types of Physical Faults

18. Faults and their Detection • Physical failures are manifested as electrical failures and are interpreted as faultson the logic level • Several physical defects may be mapped into few fault types • The main fault type is Stuck-at Fault • A fault is detected by a test pattern • Test pattern is an input combination that confirms the presence of the fault

19. Possible Defects • Two technologies, two physical defects map into the same stuck-at zero fault • Notation used - A SA0, A@0, or A/0

20. A Z B Inputs FF Faulty Response AB Response A/0 B/0 Z/0 A/1 B/1 Z/1 00 0 0 0 0 1 01 0 0 0 0 1 10 0 0 0 1 1 11 1 0 0 Detecting Stuck-at Faults Fill in the blanks in faulty response A/0 and A/1 1 1

21. Detecting Stuck-at Faults

22. Detecting Stuck-at Faults Inputs Fault Free Faulty Responses AB Response A/0 B/0 Z/0 A/1 B/1 Z/1 00 0 0 0 0 0 0 1 01 0 0 0 0 1 0 1 10 0 0 0 0 0 1 1 11 1 0 0 0 1 1 1

23. R 1 Q A S 2 Inputs Faulty Response FF Response SR A/0 S/0 R/0 A/1 S/1 R/1 01 0 0 0 X 0 0 1 00 0 1 0 X 1 0 1 10 1 1 0 1 0 1 1 11 0 0 0 1 1 1 1 Sequential Circuit

25. Types of Testing

26. Types of Tests • The exhaustive test used to detect the faults on a 2-input AND gate is not practical for circuits with 20 or more primary inputs • Pseudo-exhaustive: exhaustive for components in the circuits • segmentation or partitioning • A random test is also viable to detect faults, but pseudo-exhaustive tests are more realistic for Stuck-at Faults • Deterministic or fault oriented tests

27. Functional Testing • Exhaustive & pseudo-exhaustive testing : • Partial dependence circuits: • a circuit in which primary outputs (PO) • depend on all the primary inputs (PI) • - each output tested using 2ni inputs • (ni < n shows inputs affecting PO)

28. Functional Testing Exhaustive & pseudo-exhaustive testing Example : Exhaustive test for each gate

29. Functional Testing Exhaustive & pseudo-exhaustive testing Partitioning technique : • the circuit is partitioned into segments such that each segment has small number of inputs • each segment is tested exhaustively • usually inputs & output of each segment are not PIs or POs so we need to control segment inputs using PIs and observe its outputs using PO - this lead to sensitizing partitioning

30. Functional Testing Example : Consider the following circuit :

31. Functional Testing Example: the following shows 8 input vectors to test exhaustively h.

32. Functional Testing Example: Add vectors 5 - 8 to test exhaustively g and 9 -10 to test exhaustively y

33. Functional Testing Example: Add missing combinations to vectors 4 and 9 to test exhaustively x

34. Types of Testing • Verification testing, characterization testing • Verifies correctness of design and correctness of test procedure • May require correction of either or both • Manufacturing testing • Factory testing of all manufactured chips for parametric and logic faults, and analog specifications • Burn-in or stress testing • Acceptance testing (incoming inspection) • User (customer) tests purchased parts to ensure quality

35. Verification Test • Very expensive • Applied to selected parts • Used prior to production or manufacturing test • May comprise: • Scanning Electron Microscope tests • Bright-Lite detection of defects • Electron beam testing • Artificial intelligence (expert system) methods • Repeated functional tests

36. Manufacturing Test • Determines whether manufactured chip meets specification • Must cover high % of modeled faults • Must minimize test time (to control cost) • No fault diagnosis • Test at rated speed or at maximum speed guaranteed by supplier

38. Burn-in or Stress Test • Process: • Subject chips to high temperature and over-voltage supply, while running production tests • Catches infant mortality cases • These are damaged or weak (low reliability) chips that will fail in the first few days of operation • Burn-in causes bad devices to fail before they are shipped to customers

39. Manufacturing Test Scenarios • Wafer sort or probe test • Done before wafer is scribed and cut into chips • Test devices are checked with specific patterns to measure: • Gate threshold • Polysilicon field threshold • Poly sheet resistance, etc. • Packaged device tests

40. Types of Tests • Parametric – measures electrical properties of pin electronics – delay, voltages, currents, etc. – fast and cheap • Functional – used to cover very high % of modeled faults – test every transistor and wire in digital circuits – long and expensive http://www.ece.unm.edu/~jimp/vlsi/slides/c1_intro-8.gif

41. Functional Test • ATE and Manufacturing World – any vectors applied to cover high % of faults during manufacturing test • Automatic Test-Pattern Generation World – testing with verification vectors, which determine whether hardware matches its specification – typically have low fault coverage (< 70 %)

42. Levels of testing • Levels • Chip • Board • System • Boards put together • System-on-Chip (SoC) • System in field • Cost – Rule of 10 • It costs 10 times more to test a device as we move to higher levels in the product manufacturing process Mixed Signal VLSI Circuit

43. Levels of testing • Other ways to define levels – these are important to develop correct “fault models” and “simulation models” • Transistor • Gate • RTL • Functional • Behavioral • Architecture • Focus: Chip level testing • – gate level design

44. Typical Test Program • Probe test (wafer sort) • Catches gross defects • Contact electrical test • Functional & layout-related test • DC parametric test • AC parametric test • Unacceptable voltage/current/delay at pin • Unacceptable device operation limits

45. Rise/fall Time Tests

46. Set-up and Hold Time Tests

47. Propagation Delay Tests • Apply standard output pin load (RC or RL) • Apply input pulse with specific rise/fall • Measure propagation delay from input to output • Delay between 5 ns and 40 ns (ok) • Delay outside range (fails)

48. On Line Testing • Embedded checkers – error detection • Periodic diagnostic programs • Watchdog checkers

49. On- vs Off-Chip Testing Off chip test On chip test

50. Test Specifications & Plan • Test Specifications: • Functional Characteristics • Type of Device Under Test (DUT) • Physical Constraints – package, pin numbers, etc. • Environmental Characteristics – power supply, temperature, humidity, etc. • Reliability – acceptance quality level (defects/million), failure rate, etc. • Test plan generated from specifications • Type of test equipment to use • Types of tests • Fault coverage requirement