C to Gates Compilation: Different tools for different tasks

1. C to Gates Compilation:Different tools for different tasks Tom VanCourt Altera Corp.

2. Porting the Software Crisis to FPGAs • Edsger Dijkstra, ACM Turing Lecture 1972: The Humble FPGA Programmer • 106 LUT FPGAs coming soon • Can’t feasibly be programmed a gate at a time • More non-EE SoC developers are entering the field • Why not use familiar high level languages (HLLs)? “…the major cause [of the software crisis] is... that the machines have become several orders of magnitude more powerful! To put it quite bluntly: as long as there were no machines, programming was no problem at all; when we had a few weak FPGAs, programming became a mild problem, and now we have gigantic FPGAs, programming had become an equally gigantic problem.”

3. Implementing RTL from C description • Been around for 20+ years … but “… optimizing a sequential program onto a parallel machine has long been known to be computationally intractable … … Unfortunately, and despite 40 years of parallelizing compilers for all sorts of machines, these [optimization] algorithms don't work terribly well.” Ian Page. Compiling software to gates. 2004 • That hasn’t stopped anyone • More and more varied HLL synthesis tools than ever • More different assumptions, goals, approaches than ever • How can different tools be compared?

4. Today’s Topic: What are all these things? • What is the input representation? • More than C/C++ − Less than C/C++ • Different from C/C++ − Exactly C/C++ • What application domain? • Limited application domain vs. wide generality • Performance goals: modest acceleration to HPC • HW-specific vs. universally applicable • How integrated into tool flow? • Stand-alone block generators • “Right click to accelerate” • Synthesis, simulation, timing, … • Programming tool or synthesis tool? • Are you supposed to see every gate, every cycle?

5. Not Today’s Topic • Not a catalog of all tools on the market • Only commercial tools – not research compilers (too many!) • Examples have been chosen to represent specific features • Apologies to any vendor not represented • Not a catalog of all HLLs used for synthesis • Java, Haskell, Fortran , Lisp, … • New adaptations and new languages every day • Basic concepts applicable to any language • Not a how-to for any one tool set • None can be summarized in a 25-minute talk • Not a “which is best” comparison • I’d never leave the room alive!

6. The leastC-like … Not C at all • Example: Mitrionics’s Mitrion C • Has C in its name, but is whole new language • Handles parallelism in native language constructs • Optimizes loop structures and array accesses together • Partnered with HPC and acceleration companies: SGI, HP, Nallatech, … • To 100x speedup, in some apps • Gotchas • C code must be rewritten 100% • No floating point • OS-dependent access from host application • The only thing running in the chip • Hard to add other IP

7. The most C-like … Not C at all • Example: CriticalBlue’s Cascade • Compile machine code to gates • Input: ARM, PowerPC, MicroBlaze code • Independent of source language • Full coverage of language features (?) • Basic use model: • Compile & link, or use existing executable • Execute & profile • Tool recommends regions to accelerate • Tool creates FPGA image and binary patches to executable • Gotchas • Preserve exact order of memory references? • Good C code is almost never good logic specification • Usage restrictions (indirect branches?) not stated • 2-15× acceleration of selected kernels • Some control over resource allocation

8. Soft processor extensions • Example: Tensilica • C to gates to C • ISA extensions to soft processor • Profiling identifies hot spots • Automated generation of new instruction • Integrates instruction back into compiler, linker, debugger, simulator • Gotchas • Tensilica processor only • Generate at Tensilica server • Licensing? • Integration of other IP • C language restrictions

9. Seamless IDE integration • Example: Altera’s C2H • ANSI C with pragmas • 10-70x speedup, with tuning • Includes pointers, function pointers • Pragmas for memory binding, interrupts, connection to Avalon interconnect fabric • Replaces C function with hardware accelerator • Automatically inserts C/logic interface stubs • C function boundaries control hardware allocation, parallelism • Gotchas • No floating point • Some ANSI incompatibilities • Tied to Nios™ tool suite • Limited parallelism control

10. Whole development environment • Example: SRC’s Carte • ANSI C, Fortran • Compiler, debugger, simulator • Supports processor/FPGA partitioning • User extensions integrate with HDL generation & simulation • Platform-aware compiler enables many optimizations • Gotchas • Tied to SRC hardware • New tool flow

11. Standalone block generator • Example: Altera’s FP compiler • Small ANSI C subset • Floating point with limited library • Up to 50% reduction in latency, gate count vs. block composition • RTL interface matches C closely, input/output via global variables • Best results on complex operations with chained calculations • Some latency/logic tradeoff • Good in streaming apps • Gotchas • No if, switch, for, while • No pointers, arrays, structs • Not fully released yet, limited partner & academic licensing • Altera only

12. Specialty tool vendor • Example: Impulse C • ANSI C +/- • Adds libraries, language constructs, pragmas, data types • Emphasizes CSP computing model • Generates simulation C code • Supports partitioning, HW/SW codesign • Gotchas • Language restrictions in synthesizable subset • Need to use new library & data types for best results

13. Major EDA vendor • Example: Mentor’s Catapult • C++ with extensions • High integration with other tools, incl. synthesis SystemC modeling, mixed-level simulation • Works with technology-dependent library • Additional input specifies RTL interface • Supports fixed point analysis • Gotchas: • Only the usual: cost, learning curve, need for tuning

14. Standardized language • Example: SystemC synthesizable subset • The advantage of standards • Based on ISO C++, IEEE 1666 • Wide acceptance • Wide, interoperable tool support • Large base of C++ programmers • Vendor neutral, portable • Gotchas • It doesn’t exist • Unfortunate history • Language restrictions (e.g. subclassing) • Many previous and current attempts; not likely to match existing implementations

15. Product maturity Stability, correctness Service and support Training Documentation Sample code Developer community Chips & platforms Support latest FPGA families Cost & licensing Initial and renewal cost Royalties per unit of product Language support C, C++ language features C99, DTR 18037 Developer effort Initial learning curve Need for code tuning HW platform integration 0% for EDA, vendor tools 100% for platform vendors Mixed in many cases More to think about

16. Thanks for your attention!