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Overview of SLB ASIC

Overview of SLB ASIC. Introduction SLB Internal Structure Evaluation for Radiation Tolerance Inspection procedure in the production Plan for Mass-Production. Introduction. SLB (Slave Board) ASIC ROHM (Kyoto, J) 0.35um CMOS processed in 9.86x9.86mm 2 die

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Overview of SLB ASIC

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  1. Overview of SLB ASIC • Introduction • SLB Internal Structure • Evaluation for Radiation Tolerance • Inspection procedure in the production • Plan for Mass-Production PRR of the TGC SLB and SSW (Reported by CF)

  2. Introduction • SLB (Slave Board) ASIC • ROHM (Kyoto, J) 0.35um CMOS processed in 9.86x9.86mm2 die • Total 800Kgates (200K for random logic) • Four Blocks can be identified in the mask pattern photo • Macro-core place and routing Input Trigger JTAG Readout PRR of the TGC SLB and SSW (Reported by CF)

  3. Four Blocks Trigger Readout JTAG Input Internal Structure 20bit (+20bit) clk,BCR,ECR and x4 PRR of the TGC SLB and SSW (Reported by CF)

  4. Trigger Block: Low pT Trigger6 < pT < 20GeV/C, 3 trigger Schemes W S & EI/FI W & S 1 out of 2 3 out of 4 2 out of 3 ~EI/FI PRR of the TGC SLB and SSW (Reported by CF)

  5. Readout Block • L1Buffer: 212 input bits x 128 step shift register array • Derandomizer 212+4+2 input bits x 128 depth FIFO block • Hit data of three bunch crossings around L1A (Previous, Current and Next) are sent to ROD via SSW PRR of the TGC SLB and SSW (Reported by CF)

  6. Input and JTAG Block • Double Mask (160bit x2) StructureFour types of Mask = through, 0, 1 and Test Pulse Pattern • All the internal registers are accessible with JTAG • All the internal registers with R/W prepare so called voting logic structure PRR of the TGC SLB and SSW (Reported by CF)

  7. Evaluation for Radiation Tolerance • Measurements of Radiation Characteristics of ROHM 0.35um CMOS (presented in LECC2004) • Radiation Environment of SLB • TID test results with soft g rays from Cobalt-60 • SEE test results with proton 70 MeV PRR of the TGC SLB and SSW (Reported by CF)

  8. Radiation Environment Ionizing Dose: Gy/year 2-3Gy/10year => 140-210Gy/10year(with Safety Factor:70) Total Hadron (>20MeV) :/cm2/year 1.4-2.8x1010 hadrons/cm2/10year PRR of the TGC SLB and SSW (Reported by CF)

  9. TID test results of ROHM 0.35um CMOS PP ASIC (Leakage current vs. Dose) • TID test of Patch Panel ASIC (ROHM CMOS 0.35um) • Four Chips irradiated with g form Cobalt-60 (3 chips till 300Gy, 1 till 900Gy) • Maximum dose for SLB estimated is 200Gy. • No significant current increase has been observed till 300Gy for all the chips. PRR of the TGC SLB and SSW (Reported by CF)

  10. TID test results CMOS ROHM 0.35umPP ASIC and Ring-Oscillator ASIC • PP ASIC VCON(V) of PLL circuit for variable delay • Special Made Ring Oscillator PRR of the TGC SLB and SSW (Reported by CF)

  11. SEE Test results (with Proton 70MeV) • Instead of SLB, we have evaluated SEE of ROHM 0.35um CMOS with 4 bit 256 stage shift registers. • Total 185 soft SEE for four chips tested, no hard SEE observed with proton fluence of 6.3x1012 (protons/cm2) • sSEE = 2.8x10-14 (cm-2/bit) estimated • SEU rate = sSEE x Nbits x SRLSEEx SFsim • SRLSEE = 2.11x102 (protons/cm2/s) : Radiation Level (hadrons) at SLB • SFsim = 5 : Safety Factor (predefined) • Assume Nbits/SLB~3000, Number of SLB chips/System~3000,then SEU rate (day) in whole system ~ 25Note: this is estimated w/o voting logic PRR of the TGC SLB and SSW (Reported by CF)

  12. Inspection of products in the Production Process • More than 3000 SLB ASIC chips will be produced. • We anticipate a few % of products will have flaws either in a silicon or in a package. • 6.4% (1640 out of 25809) failure rate was observed in the PP ASIC routine test last year. • Reject them before install chips on PS-board. • An effective system and procedure must be established for the chip inspection. PRR of the TGC SLB and SSW (Reported by CF)

  13. Inspection Board & Sequence • Trigger Test • Set registers of SLB via JTAG3 • Set SLB Input pattern via JTAG1or set MASK and Test Pulse Trigger • Set DATA_LATCH_ & read Output via JTAG2 • Check Data with PC • Readout Test • Set registers of SLB via JTAG3 • Set SLB Input pattern via JTAG1or set MASK and Test Pulse Trigger • Input L1A signal from CPLD • Readout data synchronised with RCLK from SLB to CPLD • Check Data with PC PRR of the TGC SLB and SSW (Reported by CF)

  14. Inspection Procedure • Inspection must be done by routine-operators for all chips delivered. • The Test procedure planned is as follows: • Standard power-on test (current measurement) • Check of SLB register access (R/W) • Trigger output check with five different types (WD, WT, SD, ST and EI/FI) • With Different delay values • With Different coincidence conditions • Using SLB input or mask set with test pulse trigger • Readout data during the test by inputting L1A in appropriate timing, and check of data consistency. • The test frequency will be suitably determined but lower than 40MHz. PRR of the TGC SLB and SSW (Reported by CF)

  15. Plan for mass-production • We have now one working version of SLB (version so called 4ECO2). • In the end ofMarch2005 (next week), version 6 will be delivered. We then check this one, and determine which will be used for the production if version 6 works fine. If every part of version 6 works fine, this must be selected for the production. • We will make this decision in the middle of April. • We will order ROHM for production immediately. The production takes 1.5-2 months. We will get products early in June at latest. • The inspection will take a month subsequently. We complete SLB production in the beginning of August. • Overall costs for production including inspection takes \15M ~ SFr150K PRR of the TGC SLB and SSW (Reported by CF)

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