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CHAPTER 2

CHAPTER 2. Introduction to Counter By : Pn Siti Nor Diana Ismail. Outlines . (i). Asynchronous Counter (ii).Synchronous Counter. Introduction. A counter – a group of flip-flops connected together to perform counting operations.

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CHAPTER 2

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  1. CHAPTER 2 Introduction to Counter By : Pn Siti Nor Diana Ismail

  2. Outlines (i). Asynchronous Counter (ii).Synchronous Counter

  3. Introduction • A counter– a group of flip-flops connected together to perform counting operations. • The number of flip-flops used and the way in which they are connected determine the number of states (modulus). • Two broad categories according to the way they are clocked: i. Asynchronous counter – do not have fix time with each other ii. Synchronous counter – have a fix time with each other

  4. (i) Asynchronous Counter • Don’t have fixed timerelationship with each other. • Triggering don’t occur at the same time. • Don’t have a commonclock pulse

  5. Example : 2-bit Asynchronous Binary Counter

  6. Timing Diagram • Main clock pulse only applied to FF0. • Clock for next FF, taken from previous complemented output Q. • All inputs (J, K) are high (Vcc). • 2nd FF is triggered by Q0’ output of FF0. • FF0 change state at positive-going edge each clock pulse but FF1 only change state when triggered by positive-going transition of Q0’ output FF0. • Transition of clock pulse and transition of Q0’ FF0 can never occurs at same time.

  7. Timing Diagram (cont’d)

  8. Timing Diagram (cont’d) • Positive-edge CLK1 cause Q0 output FF0 HIGH at same time Q0’ goes LOW but no effect FF1 bcoz positive edge transtion must occur to trigger FF. • After leading edge CLK1, Q0= LOW, Q0’= HIGH bcoz in toggle condition. • At CLK2 cause Q0= LOW, Q0’= HIGH. It can triggered FF1 and Q1= HIGH. • After leading edge CLK2, Q0=0, Q0’=1 and Q1=1 • Positive-edge CLK3 cause Q0=HIGH bcoz JK FF in toggle mode, So the output Q0’=LOW, So FF1 no effected. • At CLK4, Q0=LOW, So Q0’=HIGH and trigger FF1, Q1=0 • After leading edge CLK4, Q0=0 and Q1=0. • Counter now recycled to origin state and both FF are RESET.

  9. Binary State Sequence Term recycled = applied to counter operation and it refer to transition of counter from it final state back to original state.

  10. Example : 3-bit Asynchronous Binary Counter and timing diagram for one cycle

  11. State sequence for a 3-bit binary counter

  12. Propagation delays in 3-bit binary counter

  13. Assignment 1

  14. Asynchronous Decade Counter • The modulusof a counter is the number of unique states that the counter will sequence through. • The maximum possible number of states (max modulus) is 2n . Where n is the number of flip-flops. • Counter can also be designed to have a number of states in their sequence that is less than the maximum of 2n. The resulting sequence is called truncated sequence. • Counter with ten states are called decade counter. • To obtain a truncated sequence it is necessary to force the counter to recyclebefore going through all of its possible states.

  15. Example : 4-bit Asynchronous decade counter

  16. (ii). Synchronous Counter Synchronous counter • - clock input connected to all FF. • - so, they are clock simultaneously.

  17. Example : 2-bit Synchronous counter Toggle (0 to 1)Toggle (1 to 0)Toggle (0 to 1)Toggle (0 to 1) Toggle (0 to 1)Toggle (1 to 0)

  18. Binary state sequence

  19. Example : 3-bit synchronous counter 0 1 0 1 0 1 0 1 0 0 0 1 1 0 0 1 1 0 0 0 0 0 1 1 1 1 0

  20. Binary state sequence for 3-bit binary counter

  21. Example : A 4-bit synchronous binary counter and timing diagram. Points where the AND gate outputs are HIGH are indicated by the shaded areas.

  22. Example : 4-bit synchronous BCD Decade counter

  23. State sequence for 4-bit synchronous BCD Decade counter

  24. QUIZ • What is application of Flip-flops?List three of them. • Name 2 categories of counter? Explain it. • Draw the waveform of 2-bit binary counter. • What is Decade Counter?

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