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Power Optimization of Real-time Systems on Variable Speed Processors

Explore the need for power reduction in real-time systems, focusing on Low Power Fixed Priority Scheduling (LPFPS) techniques for variable speed processors. Learn about power reduction methods, experimental results, and conclusion for significant power reduction.

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Power Optimization of Real-time Systems on Variable Speed Processors

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  1. Power Optimization of Real-time Systems on Variable Speed Processors Ly K. Le EE590

  2. Contents • Why need power reduction? • Low power fixed priority scheduling (LPFPS) • Overview of the approach • Sources of idle intervals • Methods of power reduction • Experimental results • Conclusion

  3. Why need power reduction? • Power consumption – a critical design constraint in real-time systems • Increase of system functionalities • Demand of long battery time NEED POWER REDUCTION!!!

  4. LPFPS Fixed priority preemptive scheduling • Rate-monotonic scheduling • Off-line priority assignment • Hard periodic deadline tasks • Widely used method in real-time systems • Simple implementation and timing analysis • Low overhead and predictability Implementation • Active task, Run Queue, Delay Queue

  5. LPFPS (cont’d) • Reduce power consumption => get rid of idle intervals in the scheduler • Identify three sources of idle intervals • Non tightly-designed system • Tightly-designed system • Variable execution time system • Data-dependent computation • Over-estimation of worst case execution time

  6. LPFPS (cont’d)

  7. Power Optimization Methods • Off-line algorithm • Determine the lowest possible maximum processor speed • Guarantee the feasibility of the scheduler • Only be applied to the periodic tasks starting at the same time • Exploit idle intervals in the non tightly-designed system

  8. Computation of the maximum processor speed Ci : worst case execution time of task i Ti: period of task i Di: deadline of task i ni: speed scaling factor of task i n: speed scaling factor of the system n = max (ni) where i = 1, 2, ….., (tasks)

  9. Computation (cont’d) • The maximum processor speed is reduced in half or task execution time is doubled

  10. Power Optimization Methods (cont’d) • On-line algorithm • Vary the processor speed or use the power-down mode • Exploit idle intervals in both tightly-designed system and variable execution time system • Save more power if both on-line and off-line algorithms are combined

  11. Power-down Mode • Conventional method: power-down after predefined idle period • Predictive system shutdown • Only clock and timers kept running

  12. Variable Processor Speed • Clock frequency is varied due to idle intervals and variable execution time • Power consumption of VSP is less than that of the constant speed processor • More variable speed rates the processor has, more power the system saves.

  13. LPFPS Implementation • Run Queue • hold tasks waiting to run • have tasks ordered in priority • Delay Queue • hold tasks already run in current period and waiting to start again in next period • Active task • task running on the processor

  14. LPFPS Implementation (cont’d)

  15. Experimental Results • Compare average power consumed by LPFPS and FPS • NOPs are assumed for idle time in FPS • Applications • Avionics, INS, Flight Control, CNC • Timing parameters given: period, deadline, WCET • Execution time variation • Control BCET: 0.1WCET  1.0WCET • Execution time of each instance of a task: random variable following Normal distribution with m = (BCET+WCET)/2,  = (WCET-BCET)/6

  16. Experimental Results (cont’d) • Architectural assumptions • NOP: 20% power consumption compared to typical instructions • Power-down mode: 5% power consumption of the fully active mode with 10 clock cycles delay • Processor model (Pering et al.) • ARM8 core-based architecture • Clock frequency: 100 MHz to 8 MHz with 1 MHz step • Supply voltage: 3.3 V to 1.1V • Delay: 10 s in worst-case

  17. Avionics INS %reduction % reduction Flight control CNC %reduction % reduction Experimental Results (cont’d)

  18. Conclusion • Propose a power optimization method for fixed priority scheduled real-time systems • Exploit both power-down mode and dynamically changing the speed of the processor • Run time mechanism is simple enough for real-time analysis and implementation • Obtains a significant power reduction across several applications

  19. References • http://poppy.snu.ac.kr/papers/iccad01_ysshin.pdf • http://www.sigda.org/Archives/ProceedingArchives/Dac/Dac2001/papers/2001/dac01/pdffiles/49_1.pdf • http://faculty.cs.tamu.edu/rabi/Technical%20Reports/CASES02-2.pdf • http://www.netrino.com/Publications/Glossary/RMA.html • http://www.sigda.org/Archives/ProceedingArchives/Dac/Dac99/papers/1999/dac99/slides/dp08_03.ppt

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