Design & Co-design of Embedded Systems

1. Design & Co-design of Embedded Systems Other Simulation Techniques in SystemC Maziar Goudarzi

2. Today Program • Advanced Simulation Control • Reactivity in SC_CTHREAD processes • FSM Modeling Techniques Design & Co-design of Embedded Systems

3. Other Simulation Techniques Advanced Simulation Control

4. Special Objects: Clocks • Clocks generate timing signals to synchronize simulation events • No clock-signal is declared • Instead, an sc_clock object is instantiated • Declaration syntax (old) sc_clock clk_name(“clk_name”, clk_period=1, clk_duty_cycle=0.5, first_edge_time=0, first_edge_type=true); Design & Co-design of Embedded Systems

5. Special Objects: Clocks (cont’d) • Declaration syntax (new) sc_clock clk(“clk”, clk_period=1, time_unit=SC_NS); • Example: sc_clock clk1(“clk1”, 10, SC_PS); • Values for time_unit argument • SC_FS, SC_PS, SC_NS, SC_US, SC_MS, SC_SEC Design & Co-design of Embedded Systems

6. Special Objects: Clocks (cont’d) • Multiple clocks are allowed • Different frequencies • Different phase relations • Declaration point • Typically generated at top-level module and passed down to lower-level modules • The clock object or its signal (i.e. clock_object.signal() ) can be passed down Design & Co-design of Embedded Systems

7. Special Objects: Clocks(cont’d) sc_clock clock("Clock", 20, 0.2, 3, false); Design & Co-design of Embedded Systems

8. Simulation Control Functions • Simulation Control • sc_start(double simulation_duration) • sc_start(double duration, sc_time_unit) • Use non-positive or novalue for duration to continue indefinitely • sc_stop() • Debugging aid • read/print signal, port, and variable values • For ports and signals: The printed value is the current value, not the value just written to it Design & Co-design of Embedded Systems

9. Simulation Control Functions (cont’d) • Simulation Control • Advanced Simulation control techniques • Instead of sc_start() use: sc_initialize();// init SystemC scheduler // Now set signals by writing values to them sc_cycle(double); // simulates signal writes, then advances simulation time by its argument value Design & Co-design of Embedded Systems

10. Simulation Control Functions (cont’d) • Example int sc_main(int, char *[]) { ... // signal declarations ... // module instantiations sc_signal<bool> clock; sc_initialize(); for (int i = 0; i <= 10; i++) { clock = 1; sc_cycle(10); clock = 0; sc_cycle(10); } } Design & Co-design of Embedded Systems

11. int sc_main(int, char*[]) { sc_initialize(); // Let the clock run for 10 cycles for (int i = 0; i <= 10; i++) clock = 1; sc_cycle(10); clock = 0; sc_cycle(10); } // Inject asynchronous reset clock = 1; sc_cycle(5); reset = 1; sc_cycle(5); clock = 0; sc_cycle(10); clock = 1; sc_cycle(5); reset = 0; sc_cycle(5); clock = 0; sc_cycle(10); // Now let the clock run indefinitely for (;;){ clock = 1; sc_cycle(10); clock = 0; sc_cycle(10); } } Example 20 5 20 Design & Co-design of Embedded Systems

12. Other Simulation Techniques Describing FSM in SystemC

13. 0 1 0 1 0 1 Start S1 S10 S101 1 0 EXPLICIT State-Machine:101 Sequence Detector Design & Co-design of Embedded Systems

14. 0 1 0 1 0 1 Start S1 S10 S101 1 0 101 Seq. Det.(cont’d) enum states { START, S1, S10, S101 }; SC_MODULE(seq_det) { sc_in_clk clk; sc_in<bool> s, reset; sc_out<bool> z; states current_state, next_state; void change_state() { z = false; if (reset) { current_state=START; return; } switch(current_state) { case START: if (s==true) next_state = S1; else next_state = START; break; case S1: ... case S10: ... case S101: z = 1; if (s==(bool)1) next_state = S1; else next_state = S10; } current_state = next_state; } // switch } SC_CTOR(seq_det) { SC_METHOD(...); sensitive_pos<<clk; } }; Design & Co-design of Embedded Systems

15. SystemC_Win output Design & Co-design of Embedded Systems

16. 101 Seq. Det.:IMPLICIT state-machine Question: How should “reset” be applied? void change_state_thread() { while (true) { z = 0; while (s==(bool)0) wait(); // 1 is detected up to now do wait(); while (s==(bool)1); // 10 is detected up to now wait(); if (s==1) z = 1; // The complete sequence (101) detected now wait(); } } Design & Co-design of Embedded Systems

17. Changes required in SC_MODULE constructor: 101 Seq. Det.: IMPLICIT state-mach. (cont’d) SC_CTOR(seq_det) { /* SC_THREAD(change_state_thread); sensitive_pos<<clk; */ SC_CTHREAD(change_state_thread, clk.pos()); } Design & Co-design of Embedded Systems

18. SystemC_Win output Design & Co-design of Embedded Systems

19. Other Simulation Techniques Modeling Reactivity in SC_CTHREAD Processes

20. Concept of Reactivity • Property of Reaction to external events • Inherent in HW => There MUST be some way to model it in any HDL • Many SW or HW-SW systems are reactive as well: • Any control systems (Chemical process control, ABS, …) • Client-Server systems (Database Engines, …) Design & Co-design of Embedded Systems

21. Concept of Reactivity (cont’d) • Things to consider • Events to react to • Type of event (Clock edge, Signal change, some condition on signals or ports, …) • Style of reaction • Waiting style • Suspend process until an event comes or some condition holds (i.e. Blocking wait) • Watching style • Do not suspend. But always WATCH if some condition holds. Then, react accordingly: e.g. Jump to a certain routine, or point of a routine. (Non-blocking wait) Design & Co-design of Embedded Systems

22. Reactivity Facilities in SystemC • Events to react to • Sensitivity lists in SC_METHOD, SC_THREAD, and clock edge in SC_CTHREAD. • Sensitivity to any event on a signal: sensitive data member of SC_MODULE • Sensitivity to positive edge of a signal: sensitive_pos data member of SC_MODULE • Sensitivity to negative edge of a signal: sensitive_neg data member of SC_MODULE • Special case of infinite loop processes (SC_THREAD, SC_CTHREAD) • Loop re-initialization, Wait for Signal condition Design & Co-design of Embedded Systems

23. Reactivity Facilities in SystemC(cont’d) • Style of reaction • Waiting style • wait() • Both SC_THREAD and SC_CTHREAD • wait_until(<signal condition>) • Only SC_CTHREAD • Watching style (Only SC_CTHREAD) • Global watching: Always done. Cannot be disabled. • Local watching: Done in certain parts of a process. Can be disabled and re-enabled (statically) Design & Co-design of Embedded Systems

24. Only defined for signals and ports of type bool Global Watching Example SC_MODULE(data_gen) {sc_in_clk clk;sc_inout<int> data;sc_in<bool> reset;void proc();SC_CTOR(data_gen){ SC_CTHREAD(proc, clk.pos()); watching( reset.delayed()==1 );} }; void proc() {if (reset == true) { data = 0;}while (true) { data = data + 1; wait(); data = data + 2; wait(); data = data + 4; wait();} } Design & Co-design of Embedded Systems

25. Global Watching in General void data_gen::proc () {// variable declarations// watching codeif (reset == true) { data = 0;}// infinite loopwhile (true) {// Normal process function} } • Notes: • all local variables lose their values. • Multiple watching is possible Design & Co-design of Embedded Systems

26. Local Watching in General W_BEGIN// put the watching declarations herewatching(...);watching(...); W_DO// This is where the process functionality goes... W_ESCAPE// This is where the handlers for the watched events// goif (..) {…} W_END Design & Co-design of Embedded Systems

27. Local Watching Example void bus::xfer() { while (true) { // wait for a new address to // appear wait_until( newaddr.delayed()); // got a new address. process it taddr = addr; datardy = false; // cannot accept new address now data8 = taddr.range(7,0); start = true; // new addr // for memory controller wait();// wait 1 clock between data// transfers data8 = taddr.range(15,8);start = false;wait();data8 = taddr.range(23,16);wait();data8 = taddr.range(31,24);wait();// now wait for ready signal// from memory controllerwait_until(ready.delayed() == true); W_BEGINwatching( reset.delayed() );// Active value of reset// will trigger watching Design & Co-design of Embedded Systems

28. Local Watching Example (cont’d) W_DO// the rest of this block is// as before// now transfer memory data// to databustdata.range(7,0) = data8.read();wait();tdata.range(15,8) = data8.read();wait();tdata.range(23,16) = data8.read();wait();tdata.range(31,24) = data8.read();data = tdata; datardy = true; // data is // ready, new addresses ok W_ESCAPEif (reset) { datardy = false;} W_END } } Design & Co-design of Embedded Systems

29. watching statements (cont’d) • Final notes • Local watching • All events have the same priority. Use nested watches to change this. • The watched signals are only sampled at the active edges of the SC_CTHREAD clock • Global watching has priority over local watching Design & Co-design of Embedded Systems

30. Today Summary • Advanced Simulation Control Techniques • Local and Global Watching • Self-study • Chapters 7, 8, and 9 of “A SystemC Primer” book Design & Co-design of Embedded Systems

31. Other Notes • Project Progress Report 1 • Today is the (postponed!) deadline • 2-3 pages, covering • List of your collected material • Summary of what you’ve done + demo of the C++ app. • Your plan for next phases and role of each person Design & Co-design of Embedded Systems