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Company Logo Below. Sign-1. Proteus Mask Synthesis - Production Qualified for 45nm Production proven for 10 years and 7 technology nodes Dual Domain simulation provides maximum flexibility Best cost-of-ownership for LRC and OPC using general purpose hardware. Sign-2 (Use same items below).
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Sign-1 Proteus Mask Synthesis - Production Qualified for 45nm • Production proven for 10 years and 7 technology nodes • Dual Domain simulation provides maximum flexibility • Best cost-of-ownership for LRC and OPC using general purpose hardware
Sign-3 PrimeYield LCC (Lithography Compliance Checking) • Built with production-proven technology used by leading Foundries and IDMs • Analysis and auto-correction links with Galaxy™ design tools • In production at major Foundry, Fabless and leading IDMs
Sign-4 Hercules PVS – Production-proven at 45nm IDM and Fabless • Fastest performance up to 12 CPUs with command processing • Fastest performance for greater than 12 CPUs with data processing • Production-proven links to design with IC Compiler and Star-RCXT
Sign-5 Synopsys TCAD / PA-DFM From Physics to Design • Accelerate innovation and time-to-market • Reduce development time and costs • Optimize performance and manufacturability • Improve yield and profitability • Raphael NXT (TCAD Solution) • Full-Chip 3D Capacitance Extractor • • Field-solver accurate capacitance extraction for critical nets, cells and blocks • • Accounts for detailed process effects predominant in deep-submicron technologies • -Seamless integration with market-leading STAR-RCXT full-chip parasitic extractor • -Flexibility to run Raphael NXT on single or multiple CPUs • Seismos (PA-DFM Solution) • Transistor-level analysis of stress and other proximity effects in strained-silicon technologies • Uses compact models derived from physics-based stress simulations • Handles complex geometric interactions beyond simple LOD model • Accurate and efficient • Seamless integration into existing design flows
VCS(r) Native Testbench (NTB) 5X Faster Performance Sign-6 • Industry leading support for SystemVerilog and OpenVera(r) • Proven VMM methodology with next-generation VMM Planner, VMM Applications and VMM Automation extensions to speed creation of robust verification environments • Power Aware Verification support to find more bugs in low-power designs • Largest portfolio of SystemVerilog-enabled, VMM-compliant VIP provided with VCS Verification Library