William Stallings Computer Organization and Architecture

1. William Stallings Computer Organization and Architecture PARTⅡ THE COMPUTER SYSTEM Chapter 3System Buses Chapter 4 Internal Memory Chapter 5 External Memory Chapter 6 Input/Output Chapter 7 Operating System Support

2. PARTⅡ THE COMPUTER SYSTEM Chapter 3System Buses 3.1 Computer Components 3.2 Computer Function 3.3 Interconnection Structures 3.4 Bus Interconnection 3.5 PCI (Peripheral component interconnect)

3. Computer Components • At a top level, a computer consists of CPU, memory, and I/O components, with one or more modules of each type. These components are interconnected by bus to achieve the basic function of the computer.

4. 3.1 COMPUTER COMPONENTS • Von Neumann architecture • Stored Program concept • Data and instructions are stored in a single read-write memory. • The contents of this memory are addressable by location, without regard to the type of data contained there. • Execution occurs in a sequential (unless explicitly modified) from one instruction to the next.

5. Program Concept • Hardwired program • the process of connection together the various components in the desired configuration as a form of programming, called hardwired program. • Inflexible • Instead of re-wiring, supply a new sequence of codes, called programming in software, as shown in figure 3.1 (p54). • General purpose hardware can do different tasks, given correct control signals

6. Figure 3.1 Hardware and Software Approaches

7. What is a program? • A sequence of steps • For each step, an arithmetic or logical operation is done • For each operation, a different set of control signals is needed

8. Function of Control Unit • For each operation a unique code is provided • e.g. ADD, MOVE • A hardware segment accepts the code and issues the control signals

9. Computer Components • Central Processing Unit (CPU) • The Control Unit and the Arithmetic and Logic Unit (ALU) constitute the Central Processing Unit (CPU) • Main memory • Temporary storage of code and results is needed • Input/output • Data and instructions need to get into the system and results out

10. Computer Components:Top Level View MAR specifies the address in memory for the next read or write; MBR contains the data to be written into memory or receives the data read from memory; I/OAR specifies a particular I/O device. Program Counter (PC) :Address of the next Instruction Instruction Register (IR) : Instruction Being Executed Accumulator (AC): Temporary Storage

11. 3.2 COMPUTER FUNCTION Instruction Cycle • Two steps: • Fetch • Execute • Program execution consists of repeating the process of instruction fetch and instruction execution.

12. Fetch Cycle • Program Counter (PC) holds address of next instruction to fetch • Processor fetches instruction from memory location pointed to by PC • Increment PC • Unless told otherwise • Instruction loaded into Instruction Register (IR) • Processor interprets instruction and performs required actions

13. Execute Cycle • Processor-memory • data transfer between CPU and main memory • Processor- I/O • Data transfer between CPU and I/O module • Data processing • Some arithmetic or logical operation on data • Control • Alteration of sequence of operations • e.g. jump • Combination of above

14. Fig. 3.4 Characteristics of a Hypothetical Machine 0 3 4 15 Opcode Address (a) Instruction Format 0 1 15 S Magnitude (b) Integer Format 0001=Load AC from Memory 0010= Store AC to Memory 0101=Add to AC from Memory (d) Partial List of Opcodes

15. Example of Program Execution P57 Figure 3.4 1. The PC contains 300, the address of the first instruction. This instruction is loaded into the instruction register, IP. 2. The first 4 bits in the IR indicate that the AC is to be loaded. The remaining 12 bits specify the address, which is 940. 3. The PC incremented and the next instruction is fetched. 4. The old contents of the AC and the contents the AC and the contents of location 941 are added and the result is stored in the AC. 5, 6

16. Instruction Cycle - State Diagram • Instruction address calculation (iac): Determine the address of the next instruction to be executed. • Instruction fetch (if): Read instruction from its memory location into the processor. • Instruction operation decoding (iod): Analyze instruction to determine type of operation to be performed and operand(s) to be used. • Operand address calculation (oac) • Operand fetch (of) • Data operation (do) • Operand store (os)

17. Interrupts • Mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processing • Classes of Interrupts ◊Program • e.g. overflow, division by zero ◊Timer • Generated by internal processor timer • Used in pre-emptive multi-tasking ◊I/O • from I/O controller ◊ Hardware failure • e.g. memory parity error

18. 补充: 中断系统 1. 中断概念的引入 • 现行程序执行时, 首先通过输入接口启动输入设备工作. • CPU执行现行程序并等待中断 • 输入设备组织了一个数据存入输入接口电路 • 接口电路向CPU发出“中断请求”, 请求CPU中断现行程序. • CPU满足一定条件后,向接口发出中断响应信号. • CPU中断现行程序,转向预先设计好的”中断服务程序”. • CPU执行服务程序,从接口电路中取走输入数据. • 中断服务程序执行完毕,返回现行程序的断点,继续执行被中断的程序 图 运用中断技术输入数据的示意图

19. 补充: 中断向量的引导作用 • If interrupt pending: • Suspend execution of current program Save context • Set PC to start address of interrupt handler routine • Process interrupt • Restore context and continue interrupted program 图. 中断向量的引导作用

20. Transfer of Control via Interrupts

21. Program Flow Control Figure 3.7 illustrates the user program performs a series of WRITE calls interleaved with processing.

22. Figure 3.7 Program Flow of control(a) No Interrupt • The WRITE calls are to an I/O program that is a system utility and that will perform the actual I/O operation. • I/O program • A sequence of instructions, labeled 4 in the figure, to prepare for the actual I/O operation. This may include copying the data to be output into a special buffer and preparing the parameters for a device command. • The actual I/O command. Without the use of interrupts, once this command is issued, the program must wait for the I/O device to perform the requested function. The program might wait by simply repeatedly performing a test operation to determine if the I/O operation is done. • A sequence of instructions, labeled 5 in the figure, to complete the operation. This may include setting a flag indicating the success or failure of the operation

23. Figure 3.7 Program Flow of control(b) Interrupts: short I/O Wait • With interrupts, the processor can be engaged in executing other instructions while an I/O operation is in progress. • A WRITE call is the I/O program that is invoked in this case consists only of the preparation code and the actual I/O command. • When the external device becomes ready to be serviced, that is , when it is ready to accept more data from the processor: the I/O module for the external device sends an interrupt request signal to the processor. The processor responds by suspending operation of the current program, branching off to a program to service that particular I/O device (known as an interrupt handler), and resuming the original execution after the device is serviced. The points at which such interrupts occur are indicated by an asterisk in Figure 3.7b

24. Figure 3.7 Program Flow of controlwith interrupts • Figure (b) Interrupt: short I/O Wait • assumes that the time required for the I/O operation is relatively short: less than the time to complete the execution of instructions between operations in the user program. • Figure (c) Interrupt: long I/O Wait • indicates that the user program reaches the second WRITE call before the I/O operation spawned by the first call is complete. The result is that the user program is hung up at that point.

25. Figure (c) Interrupt: long I/O Wait • indicates that the user program reaches the second WRITE call before the I/O operation spawned by the first call is complete. The result is that the user program is hung up at that point.

26. Figure 3.10 Program Timing: Short I/O Wait

27. Figure 3.10 Program Timing: Long I/O Wait · · The timing for this situation with interrupts has a gain in efficiency because part of the time during which the I/O operation is underway overlaps with the execution of user instructions

28. Interrupt Cycle • Added to instruction cycle • Processor checks for interrupt • Indicated by an interrupt signal • If no interrupt, fetch next instruction • If interrupt pending: • Suspend execution of current program • Save context • Set PC to start address of interrupt handler routine • Process interrupt • Restore context and continue interrupted program

29. Instruction Cycle (with Interrupts) - State Diagram

30. Multiple Interrupts • Disable interrupts • Processor will ignore further interrupts whilst processing one interrupt • Interrupts remain pending and are checked after first interrupt has been processed • Interrupts handled in sequence as they occur • The drawback is that it does not take into account relative priority or time-critical needs. • Define priorities • Low priority interrupts can be interrupted by higher priority interrupts • When higher priority interrupt has been processed, processor returns to previous interrupt

31. Multiple Interrupts - Sequential (a) Sequential Interrupt Processing

32. Multiple Interrupts - Nested (b) Nested Interrupted Processing

33. Time Sequence of Multiple Interrupts

34. 3.3 INTERCONNECTION STRUCTURES • All the units must be connected • Different type of connection for different type of unit (Figure 3.15) • Memory • Input/Output • CPU

35. Computer Modules

36. Memory Connection • Receives and sends data • Receives addresses (of locations) • Receives control signals • Read • Write • Timing

37. Input/Output Connection(1) • Similar to memory from computer’s viewpoint • Output • Receive data from computer • Send data to peripheral • Input • Receive data from peripheral • Send data to computer

38. Input/Output Connection(2) • Receive control signals from computer • Send control signals to peripherals • e.g. spin disk • Receive addresses from computer • e.g. port number to identify peripheral • Send interrupt signals (control)

39. 补充: 输入/输出端口 端口/口: 接口电路中包含的一组能与CPU交换信息的寄存器，称为I/O端口寄存器或端口。端口分为三类： 1．数据端口:用于存放数据信息（通常为8位或16位） 输入过程：数据由外设→数据端口→数据总线DB→CPU 输出过程：数据从CPU→数据总线DB→数据端口经数据线→外设。 2．状态端口: 存放外设当前工作状态的信息. 作为一种输入数据CPU可读取。 输入接口电路——反映输入数据是否准备好。 输出接口电路——反映输出设备的忙、闲状态。 3．控制端口: 存放控制信息。作为一种输出数据由CPU通过接口电路→外设，控制外设工作。 接口:若干端口加上相应控制电路.

40. 补充: 端口地址 当计算机系统中有多个外设时，CPU在某个时刻只能与一个外设打交道。为了确定此刻哪一个外设可以与计算机打交道，采取与内存同样的处理方法，利用二进制编码为外设编号，该编号被称为外设地址(又称I/O地址 / 端口地址) 。 多外设情况下,CPU通过为每个外设规定不同的地址来管理外设.因外设是通过I/O接口的端口与系统相连,故对外设寻址,实为与外设相连的I/O接口的相应端口寻址. CPU寻址的是端口寄存器.

41. CPU Connection • Reads instruction and data • Writes out data (after processing) • Sends control signals to other units • Receives (& acts on) interrupts

42. 3.4 BUS INTERCONNECTION • Bus is a shared transmission medium. • A bus that connects major computer components ( processor, memory, I/O) is called a system bus.

43. Buses • There are a number of possible interconnection systems • Single and multiple BUS structures are most common • e.g. Control/Address/Data bus (PC) • e.g. Unibus (DEC-PDP)

44. What is a Bus? • A communication pathway connecting two or more devices • Usually broadcast • Often grouped • A number of channels in one bus • e.g. 32 bit data bus is 32 separate single bit channels • Power lines may not be shown

45. Data Bus • Carries data • Remember that there is no difference between “data” and “instruction” at this level • The number of lines (the width of the data bus) determines how many bits can be transferred at a time. • Width is a key determinant of system performance • 8, 16, 32, 64 bit

46. Address bus • Identify the source or destination of data • e.g. CPU needs to read an instruction (data) from a given location in memory • Address Bus width determines maximum memory capacity of system • If bus address width is x bits, the maximum memory capacity is 2x. • e.g. 8080 has 16 bit address bus giving 64k address space

47. Control Bus • Control and timing information • Timing signals indicate the validity of data and address information. Command signals specify operation to be performed. • Typical control lines • Memory read/write signal • I/O write/read • Interrupt request • Interrupt ACK • Bus request: Indicates that a module needs to gain control of the bus • Bus grant: Indicates that a requesting module has been granted control of the bus • Transfer ACK: Indicates that data have been accepted from or placed on the bus • Clock signals: used to synchronize operation • Reset: Initializes all modules • Clock: Used to synchronize operations

48. Bus Interconnection Scheme

49. Big and Yellow? • What do buses look like? • Parallel lines on circuit boards • Ribbon cables • Strip connectors on mother boards • e.g. PCI (Peripheral Component Interconnection ) • Sets of wires

50. Single Bus Problems • Lots of devices on one bus leads to: • Propagation delays • This delay determines the time it takes for devices to coordinate the use of the bus. • Long data paths mean that co-ordination of bus use can adversely affect performance • The bus may become a bottleneck as a aggregate data transfer approaches bus capacity • Most systems use multiple buses to overcome these problems