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. . Addressing Modes: Specifying the Operands. ImmediateDirectIndirectRegisterRegister IndirectDisplacement (Indexed) Stack. . . Immediate Addressing. Operand is part of instructionOperand = address fielde.g. ADD 5Add 5 to contents of accumulator5 is operandNo memory reference to fetch d
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1. William Stallings Computer Organization and Architecture Addressing Modes
and Formats (Chapter 10)
2. Addressing Modes: Specifying the Operands Immediate
Direct
Indirect
Register
Register Indirect
Displacement (Indexed)
Stack
3. Immediate Addressing Operand is part of instruction
Operand = address field
e.g. ADD 5
Add 5 to contents of accumulator
5 is operand
No memory reference to fetch data
Fast
Limited range Where does immediate operand come from : compiler / assembler Where does immediate operand come from : compiler / assembler
4. Immediate Addressing Diagram How do we differentiate between normal immediate data and other stuff (special symbols $ # %)How do we differentiate between normal immediate data and other stuff (special symbols $ # %)
5. Direct Addressing Address field contains address of operand(not its content)
Effective address (EA) = address field (A)
e.g. ADD A
Add contents of cell A to accumulator
A symbolizes an address in memory (or I/O )
Look in memory at address A for operand (at exec. time)
How do we know if A symbolizes an address ?
Single memory reference to access data
No additional calculations to work out effective address
Limited address space Effective address: address of the final actual operand you want !Effective address: address of the final actual operand you want !
6. Direct Addressing Diagram
7. Indirect Addressing (1) Memory cell pointed to by address field contains the address of (pointer to) the operand
EA = (A)
Look in A, find address (A) and look there for operand
e.g. ADD (A)
Add contents of cell pointed to by contents of A to accumulator
8. Indirect Addressing Diagram
9. Immediate Addressing Diagram Opcode may contain the mode in it (effectively different instructions)Opcode may contain the mode in it (effectively different instructions)
10. Direct Addressing Diagram
11. Indirect Addressing (2) Large address space
2n where n = word length
May be nested, multilevel, cascaded
e.g. EA = (((A)))
Draw the diagram yourself
Multiple memory accesses to find operand
Hence slower
12. Register Addressing (1) Operand is held in register named in address filed
EA = R
Limited number of registers
Very small address field needed
Shorter instructions
Faster instruction fetch
13. Register Addressing (2) No memory access
Very fast execution
Very limited address space
Multiple registers helps performance
Requires good assembly programming or compiler writing
N.B. C programming
register int a;
c.f. Direct addressing
14. Register Addressing Diagram
15. Register Indirect Addressing C.f. indirect addressing
EA = (R)
Operand is in memory cell pointed to by contents of register R
Large address space (2n)
One fewer memory access than indirect addressing
16. Register Indirect Addressing Diagram
17. Displacement Addressing EA = A + R
Address field hold two values
A = base value
R = register that holds displacement
or vice versa
Variations possible: (A) + R,
Convenient for accessing memory elements off a boundary (array[8])Variations possible: (A) + R,
Convenient for accessing memory elements off a boundary (array[8])
18. Displacement Addressing Diagram
19. Relative Addressing A version of displacement addressing
R = Program counter, PC
EA = A + PC
i.e. get operand from A cells from current location pointed to by PC
c.f locality of reference & cache usage
20. Base-Register Addressing A holds displacement
R holds pointer to base addressEA = (R) + A
R may be explicit or implicit
e.g. segment registers in 80x86
21. Indexed Addressing A = base
R = displacement
EA = A + R
Good for accessing arrays
EA = A + R
R++
= displacement
Displacement = amount off the memory bound ? ??
Indexed: counter ? ?? but same after all= displacement
Displacement = amount off the memory bound ? ??
Indexed: counter ? ?? but same after all
22. Combinations Post-index (c.f. x++ in C)e.g. EA = A + R, R = R + index
Pre-index (c.f. ++x in C)e.g. R = R + index, EA = A + R
All the variations you can think of
23. Stack Addressing Operand is (implicitly) on top of stack
Zero address instruction / machine
Where does the result go ?
Somewhere fixed (like top of the stack !)
e.g.
ADD Pop top two items from stack and add, place result on top of stack
Compatibilty of operands byte instruction needs byte quantity Compatibilty of operands byte instruction needs byte quantity
24. Instruction Formats Layout of bits in an instruction
Includes opcode
Includes (implicit or explicit) operand(s)
Usually more than one instruction format in an instruction set ? need mode
One mode (usually) for each operand ? because we want to designate an addressing mode for each operand
Mode information may be included in the instruction type
E.g. ADDI 4,A ; add immediate to direct address
25. 16 bit (2 bytes)
orthogonal: most instructions will work with this format (every opcode can do every addressing modes)
there is no completely orthogonal architecture (but we can talk about degrees)
(compiler/assembler writers love orthogonality)orthogonal: most instructions will work with this format (every opcode can do every addressing modes)
there is no completely orthogonal architecture (but we can talk about degrees)
(compiler/assembler writers love orthogonality)
26. Motorolla 68000 18 instruction formats crammed into 16 bit opcode+mode section
Make few important instructions orthogonal
e.g. the move instruction)
so the move can do memory to memory movement
But other than that, because of the cramming, decoding this instruction is hard (from programmer's point of view, does not matter)
27. For example, Format 1 : move instructions
Format 2 : add instructions
mod determines size and dest/source, but this is only 6 combinations ...
2 other possibilities are used for completely different instruction (difficult to decode, but we do not really have to worry about this ...)
38. Instruction Length Affected by and affects:
Memory size
Memory organization
Bus structure
CPU complexity
CPU speed
Trade off between powerful instruction repertoire and saving space (CISC vs. RISC)
39. Allocation of Bits Number of addressing modes
Number of operands
Register versus memory
Number of register sets
Address range
Address granularity